Due to race conditions, ETM initialization can fail if cpu hotplug
occurs while ETM probe is ongoing. Move etmdrvdata initialization
just before put_online_cpus() to prevent this race condition.
Change-Id: Iac943e5498d30554f5cb8bca4a9fe8e32bdf4030
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
CPU id returned by raw_smp_processor_id() is guaranteed to be less than
NR_CPUS. So etmdrvdata array will never do out of bound accesses. Remove an
unnecessary if statement which validates this.
Change-Id: I4a46f488ba8583cfbc5bc44c7679fb93a6f6b09b
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Hardware sets the register values to indicate how many resources the trace
unit supports. Add checks to validate these values to avoid any out of
bounds access.
Change-Id: I5f19a1351af3bc727f6fb7743a258727fa80fc06
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Add support to retrieve CoreSight ETM funnel port for the CPU
associated with the ETM device to allow enabling and disabling
the correct funnel port to prevent trace flush hang during power
collapse.
Signed-off-by: Aparna Das <adas@codeaurora.org>
Change-Id: I880881b5d4de4bf1947e5316eb1ad624176516dd
Modify CoreSight drivers probe to remove dependency on ETM0
device to enable successful probe of other ETM devices even
when core0 is hotplugged off during boot.
Change-Id: I3a544d1e937719f1a1861aef37c2580aa2fb6b7d
Signed-off-by: Aparna Das <adas@codeaurora.org>
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Add a new attribute to show the paired cpu number of ETM.
This will be useful information for the user and can be
used for eg. to determine which logical cpu to online for
a particular ETM.
Change-Id: I3ace88606b93f93de47e1f1351d6ff5a7cd04cb4
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Add support for resetting ETM parameters by default on bootup
which can otherwise be done using sysfs.
Change-Id: I098274a44dd9150ccbf3afd88654eb0a7eb74809
Signed-off-by: Aparna Das <adas@codeaurora.org>
Add client support to register with the memory dump v2 driver to
take advantage of the new enhanced memory dump format.
Change-Id: I8b05d92b3e9f4d1dcaa6dffec8fe05401d72a7ee
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
General cleanup to avoid global name space clashes. This is in
preparation for the memory dump v2 driver.
Change-Id: I884ff3a06c74166dc0cd9004085ab9b43646ef6a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Architectural changes in the ARM Linux kernel tree mandate
the eventual removal of the mach-* directories. Move the
memory dump driver to drivers/soc/qcom and the memory dump header
to include/soc/qcom to support that removal.
Change-Id: If04f6a4fcd30c864321ac0ff8c6691fc20707cc1
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Signed-off-by: Aparna Das <adas@codeaurora.org>
Upstream prefers existing drivers be converted to support multiplatform
kernels. This requires drivers to be located in directories that
contain generic functionality instead of specific mach directories.
Move the socinfo driver into drivers/soc/qcom and update the initcall
levels to satisfy dependencies.
Change-Id: If195cd793d84867d371f25136a88f2a7ce239500
Signed-off-by: Xiaocheng Li <lix@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Add support to query CoreSight fuse state and fail the probe
if any of the required fuse(s) are disabled. This enables
a single image with CoreSight drivers compiled in to be run on
both Hardware that has CoreSight functionality disabled via fuse
or left enabled for use.
Change-Id: Ib770cc7f76e2b0644bda9600c92fc3a26823452d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Calling register_hotcpu_notifier inside of get/put_online_cpus
i.e. after taking the cpu_hotplug lock results in a deadlock
since register_hotcpu_notifier takes the cpu_add_remove_lock
which has already been acquired by the hotplug code before
requesting the cpu_hotplug lock.
Remove the get/put_online_cpus calls since they are not required.
CRs-Fixed: 501374
Change-Id: I3fb58265f6fedeb696d035d281af0d7904e28b79
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Vote for enabling clocks during hotplug ON in CPU_UP_PREPARE and
correspondingly vote to disable clocks in CPU_ONLINE or
CPU_UP_CANCELED callbacks until OS lock is unlocked. This is
required since memory mapped accesses to unlock the OS lock as
part of CPU_STARTING callback for some ARM based cpus need the
appropriate clocks to be on.
Change-Id: Ia9709692beb02654c225a0771c1eea556d581372
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Modify coresight drivers to perform resource lookup by name. The
coresight drivers now use the reg-names property specified in dt
nodes to lookup for resources.
Change-Id: I986f9687be81706d2424e288b9875c3a93e12d11
Signed-off-by: Aparna Das <adas@codeaurora.org>
On CPUs which implement OS lock mechanism, the ETM driver needs to unlock
the OS lock in order to configure ETM registers. Implement OS unlock on
CPUs using a memory mapped access instead of cp14. This is necessary on
CPUs which implement OS lock mechanism and provide only memory mapped
accesss to ETM registers.
Change-Id: I1559cc32e77a5d3cd42badf4f81ca253cd316f5d
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Krait v4 only supports cp15 CPMR_ETMCLKEN for turning on ETM
power/clock for subsequent cp14 accesses so use it instead of
ETMPDCR. Other Kraits also support cp15 CPMR_ETMCLKEN for turning
on ETM power/clock so it can be safely used for all Kraits.
Change-Id: I404b96d84a3c9329bf9a571db7ce57b91d9dc76c
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Change CONFIG_MSM_QDSS to granular CORESIGHT configs covering
various CoreSight drivers. This better represents the CoreSight
device topology and allows more flexibility in choosing the
drivers required for a particular platform or chip.
Change-Id: I5ae44442c24c88673f2045ad24dc89e4d86d23cb
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
When ETM is enabled via kernel command line or config item but we
boot with maxcpus parameter value of less than number of present
cpus, cpus that are not included as part of maxcpus don't
get ETM enabled during kernel init since those cpus would not be
online.
This change ensures that for such cpus, first hotplug after the
respective cpu's ETM probe is done, enables ETM if it is enabled
via kernel command line or config item but hasn't already been
enabled.
Change-Id: Ie3613819896e781732b80d6be20f930b474418e8
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Enable and disable ETM during hotplug operations only if ETM is
allowed round-robin access by the funnel when all the ETMs share
the same funnel priority.
For 8960, 8064, etc it is observed that sometimes a core's ETM is
starved by other core ETMs constantly producing data. This works
around an issue seen where setting the prog bit of a core's ETMCR
(i.e. ETMCR[10]) doesn't result in that core's ETMSR[1] getting
set thereby triggering the "timeout while setting prog bit"
warning. Subsequently performaing a manual ETB flush as part of
disabling ETB to retrieve the collected trace data also fails.
Change-Id: I6dd37979058644495d945e80e6a2de4696fc5a20
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
smp_calls are cpu hotplug safe and so cpu hotplug locking isn't
required to safeguard them. Remove get_online_cpus() and
put_online_cpus() cpu hotplug locking calls that are currently
safeguarding smp_calls against cpu hoplugging.
Change-Id: I527403f4ffe088f3ee65b0b0899b398e1449ab48
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
MSM9625 implements ETM based on ETM version 3.5.
As such the 9625 ETM registers need some additonal configuration
for ETM to be functional. They also have some extra registers which
need to be configured properly while some registers currently being
configured by the driver are absent on 9625. Additonally, the ETMv3.5
can be configured to support data tracing, support for which is
not present in the existing ETM driver.
Change-Id: Ic3e61d0d1abf371653a398a28111b308747a7b6f
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
When PC save is enabled via kernel command line or config item
but we boot with maxcpus parameter value of less than number of
present cpus, cpus that are not included as part of maxcpus don't
get PC save feature enabled during kernel init since those cpus
would not be online.
This change ensures that for such cpus, first hotplug after the
respective cpu's ETM probe is done, enables PC save feature if
the feature is enabled via kernel command line or config item but
hasn't already been enabled.
Change-Id: I9cae33654539ed72885fdf11cd603c7c776512c1
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Having both both ETMPDCR[3] set and ETMCR[0] cleared causes
pre-mature resumes from suspend power collapse. For now, clear
pwrup (ETMPDCR[3]) right after clearing pwrdwn (ETMCR[0]) to
avoid pre-mature resume from suspend power collapse.
Change-Id: I4b951ecc672d42aa9ea1feb7a5f999d24698405e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Fail ETM enable if the core is offline so that it is obvious to
the user that the operation failed. ETM disable cannot fail so
disable ETM during hotplugg off if it is user enabled and
re-enable ETM during hotplugg on if it is user enabled.
Change-Id: I24120582ff6d3c5f3598baff962dc2ef910c3a1e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Switch to using spinlocks instead of mutexes to make apis
callable from atomic context.
Change-Id: I6c249b66c7f9db3d6028f1ab92bacfbcf43b150e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Fail pcsave enable/disable if the core is offline so that it is
obvious to the user that the operation failed.
Change-Id: I2bd88636e1982a7de6b14f8b742d1f9bc7d23406
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Always clear ETMCR[pwrdwn] while enabling trace. This is used as
a logic enable and is a pre-requisite while enabling trace. So
switch to an implementation that does this and removes the save
and restore for pwrdwn and pwrup.
Change-Id: I8a14efe8fd76368ed1e177a701013a504aa1876f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add runtime control for enabling/disabling program counter save feature.
Enabling program counter save feature will enable pc to be saved on
reset but implies ETM being left powered on. So we provide user runtime
control to enable the feature when debugging or disable it while taking
power measurements.
Change-Id: Ib007da851ee7f3b0fac195da62aac7def68cc67a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Explicitly clear and set ETMCR power down bit as part of the ETM
register programming sequence since if this bit is set, writes to
some registers and fields might be ignored.
Moreover, ETMCR prog and power down bits are not directly modifiable
via the sysfs based MODE selction code. Instead they can implicitly get
modified by other code. So always preserve their values while
enabling ETM trace since the ctrl is a shadow of ETMCR bits that
are only modifiable via the sysfs based MODE selection code.
Change-Id: I842a42acdafb112759a1787ec6fc41140812020d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Use cp14 accesses to ETM registers for Krait v3 to avoid
limitations with memory mapped accesses.
Change-Id: Ia956eb0f5b45c748ffb5dd13dd14dc9595b9c68a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Use ETMPDCR instead of ETMCR for ETM power/clock enable/disable. ETMPDCR
doesn't have corresponding cp14 access and hence will help with subsequent
multicore ETM support changes for 8974. ETMPDCR is available for PFTv1.1
and ETMv3.5 compliant ETM implementations.
Change-Id: I4b190b963cda29b406971cf075db36213b140495
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Move etm_arch_supported out of etm_init_arch_data to simplify the
init flow.
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Change-Id: I8a95f59e35e74c5af8c447abdc9f0dcd1682bce1
Add support to allow debug image to be able to dump ETF content
and ETM, TMC regsiters in case of apps proc bite or system hang
causing secure watchdog reset.
This will enable host parsing scripts to extract ETF and
ETR-memory trace data contents from RAM dumps.
Change-Id: Ie6f03bef7b4ccda7ea8d7709ee0c4808424c5b92
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Since we moved to separate enable nodes for each ETM, using pm_qos
to prevent power collapse of the target cpu while we enable or
disable ETM is less efficient and also susceptible to a race with
cpu hotplug.
Move to using smp call to enable and disable trace to avoid above
deficiencies with the newly re-structured code.
Change-Id: I65c726dbd6275af8db0d40db5034299287a02e91
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
With maxcpus=1, only core0 will be running with other cores in
reset until they are explicitly hotplugged on. To avoid reading
ETM registers for cores that are in reset during probe, use only
ETM0 for populating configuration info. For other ETM probes,
copy the info from ETM0.
Change-Id: I9ae4539b004956a026e919323413f9e3c7d5ba4a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Bottom 8 bits [7:0] of ETMSYNCFR are reserved on Krait pass3. This
means only bits [11:8] are valid since bits [31:12] are specified
as reserved by PFTv1.1 specification.
Use an appropriate value for the synchronization frequency in light
of this change on Krait pass3.
Change-Id: I5f32ad6546fc8a72e0a222cc90e0f23c9779ee3c
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Support for reading hardware data for CoreSight devices from device
tree.
Change-Id: I4d149991c89b458384465d163386084f500a4028
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Using devm_* apis helps in simplifying driver init and exit paths,
hence switch to using them in the driver probe calls.
Change-Id: I41aba1129f6638fcee859e57f957fa3f14c1c439
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Switch all CoreSight drivers to start using the new CoreSight core
layer code. Remove obsolete qdss code.
Change-Id: I2d4496aea0ffd918e0bfbf4b4e58ad82ea634a59
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Complete the rename by changing cs to coresight for variables,
functions and constants.
Change-Id: I506d5872e5c09f201c4f3674d7722d36eca26921
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Since cs is not a well known acronym for CoreSight, rename
directory and files from cs to coresight.
Change-Id: I5f9b12794b80b1c01c9ce0621d53ee6be408a361
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Xiaogang Cui