strlen is often used incorectly to get the length of strings
defined at compile time. In these cases, the behavior can be
replicated with sizeof(X) - 1, which is calculated at compile
time rather than runtime, reducing overhead. I've created a
simple macro to replace these instances and applied it to all
the files compiled into the angler kernel.
Signed-off-by: Joe Maples <joe@frap129.org>
'commit 734aabed17090: ("coresight: tmc: Fix use after free issue
with tmc read")' adds lock in tmc_read() to fix race condition seen in
reading tmc buffer and enabling the device.But commit has unbalanced
lock. This patch fixes the lock.
Bug: 64453422
Change-Id: Iaf3ecd83ef5af346725885ea2c84c4185f1a1c50
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
Fix race condition seen between reading tmc buffer and enabling
the device. The race condition can result in a use after free
issue if the buffer is released while a read is in progress.
Bug: 64453422
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
Change-Id: I9908fa78acbf3152ee791c63fef525f09a9a23d5
Add available_out_modes and available_mem_types device attributes to
provide information on available out modes and memory type options
supported for TPIU and TMC configurations.
Change-Id: Iec02c42877aa75f024590bf112d1c33eb4ad5e46
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Add support to prevent trace flush hang during power collapse
by ensuring trace data is flushed and funnel port is disabled
before CPU is powered down.
Change-Id: I78907c40bcb9e237b6fa4e319013d478751f55da
Signed-off-by: Aparna Das <adas@codeaurora.org>
We should be using %pa when printing physical addresses. There is an
instance in the coresight code where we're casting a physical address to
a (void *) and printing that with %p. That doesn't work with LPAE since
virtual addresses are only 32-bits and physical addresses are
64-bits. Fix this.
This fixes the following warning:
In file included from kernel/drivers/coresight/coresight-tmc.c:17:0:
kernel/drivers/coresight/coresight-tmc.c: In function \
‘tmc_etr_sg_compute_read’:
kernel/drivers/coresight/coresight-tmc.c:1473:21: warning: cast to \
pointer from integer of different size [-Wint-to-pointer-cast]
error, forbidden warning: coresight-tmc.c:1473
Change-Id: I749a7650534c8cfcba45ffd49caf96d30494009b
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
The compiler thinks that phys_pte could be used uninitialized (if
sg_tbl_num == 0). Fix this.
The specific warning being fixed is:
drivers/coresight/coresight-tmc.c: In function 'tmc_read':
drivers/coresight/coresight-tmc.c:1411:14: warning: 'phys_pte' may \
be used uninitialized in this function [-Wuninitialized]
error, forbidden warning: coresight-tmc.c:1411
Change-Id: Id26d5ccc8230dc5409c53dc14925ec9067d3dd02
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Free the entire scatter gather table if buffer allocation fails for any
entry while populating scatter gather table.
Change-Id: Ifa1135b6475bd54300536d9f46f10fb9f3681f2f
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Some functions may need to know the pipe memory type, whether it
is allocated memory or a private region of internal peripheral
memory. Add an extra parameter to the get_bam2bam_connection_info()
function to return this value based on the preconfigured BAM pipes.
For most functions this info is unneeded. For QDSS, use this value
to determine whether to pass MSM_INTERNAL_MEM to the SPS params
when running on a device that requires it.
Change-Id: Ia9f5630b08a90cb66489a11707919d1855c36ec9
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Currently we read the TMC ETF contents and copy them to DDR until
the end marker is seen. If for some reason HW doesn't provide the
end marker, this can result in memory corruption since the code
will end up in an infinite loop that keeps copying contents
beyond the TMC ETF buffer.
Add an additional check to stop copying TMC ETF contents to DDR
when buffer size is reached even if end marker is not seen due to
a potential HW misbehavior.
CRs-Fixed: 671604
Change-Id: I5a6ec1231371737b8e8c368ded75f5e73ac66095
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Memory dump v2 format uses magic number that is different from
what is used with earlier version. Add support for this change
so that the TMC ramdump can be correctly parsed.
Change-Id: Ib7f5478812e59a44c609fc433e8c742fe30488a9
Signed-off-by: Aparna Das <adas@codeaurora.org>
Change flush input signal from pre_ares to flush_etr. For ETF
to be consistent with the usage model for both ETF and ETR.
Remove property reset-flush-race which is a workaround for
MSM8974v1.
Change-Id: I077f5215e75024e484abb3b68d67372ae6ccd154
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Byte counter interrupt feature provides an interface to set byte counter
value and collect continuous trace data stream from userspace. Add support
to read this trace data stream when scatter gather feature is enabled for
TMC ETR configuration.
Change-Id: Ic755b7ae14b4bf13f7f28897ec8827476366eaf7
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Add driver support to enable scatter-gather feature with TMC configuration.
Scatter gather option for ETR DDR mode supports the use of a table of
locations of 4K blocks of physical memory. Since this memory is not
necessarily contiguous, user can increase the trace buffer size as long as
DDR memory is available.
Default memory option is "contig" for TMC ETR DDR configuration. User can
enable scatter gather feature dynamically.
Change-Id: I74136fb86fe751aa33607d3922dce5d572f0a4a2
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Based on sg-enable DT entry, enable scatter gather feature
for TMC ETR configuration. Scatter gather feature is not supported
on all targets. sg-enable entry will help to enable this feature
only on those targets which supports this feature.
Change-Id: I66fe50c653ad9646104b9dc0d77a0fa6f82503dd
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Add device attribute for memory type option with TMC ETR DDR configuration.
This is in preparation for scatter gather feature with TMC ETR
configuration.
Change-Id: If72078f89442e9c58e09392fbced362126dd15e7
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Add client support to register with the memory dump v2 driver to
take advantage of the new enhanced memory dump format.
Change-Id: I8b05d92b3e9f4d1dcaa6dffec8fe05401d72a7ee
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
General cleanup to avoid global name space clashes. This is in
preparation for the memory dump v2 driver.
Change-Id: I884ff3a06c74166dc0cd9004085ab9b43646ef6a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
When byte counter feature is enabled, if the rate at which we receive IRQs
is so high that userspace is unable to read the data fast enough, we
throw byte counter overflow error message. However these messages can cause
log spew resulting in watchdog bark/bite. Limit byte counter overflow
message spew by using rate limited function.
Change-Id: I714323893330368965f70a137aaef7ef7cd4029d
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Change the bam handle data type from u32 to
unsigned long to match sps connect source
and destination.
Change-Id: I55ce477a40e4ab3d1306f8afd1acf491c22874e9
Signed-off-by: Sujeet Kumar <ksujeet@codeaurora.org>
Dynamically allocate ETR DDR memory so that user can specify
trace buffer size at runtime.
Change-Id: I081b017fa147d7c87789cc504cd9b61b7365c79f
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
As part of moving the headers from mach directory
to a common location compilation issues are arising.
Make the changes which are relevant for USB with
its own header files and also dependent header
files.
Change-Id: Ieef7d04ffdfda249f434e0676fec6da8d8b9cf2c
Signed-off-by: Sujeet Kumar <ksujeet@codeaurora.org>
Add device attribute to control ETR DDR memory size dynamically
for TMC configuration. This will help users to specify DDR trace
buffer size at runtime.
Change-Id: Ie1edef7f972435193c96dafb8a94fd6cce97ce6c
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Architectural changes in the ARM Linux kernel tree mandate
the eventual removal of the mach-* directories. Move the
memory dump driver to drivers/soc/qcom and the memory dump header
to include/soc/qcom to support that removal.
Change-Id: If04f6a4fcd30c864321ac0ff8c6691fc20707cc1
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Signed-off-by: Aparna Das <adas@codeaurora.org>
Remove the sps header file from older location as sps
driver and clients need to use new header file from
new location include/linux.
Resolve the warnings/errors from client drivers due to
new sps header changes.
Change-Id: I1cdb87756abf3425a9bb5d8bf89cd1aa03a01716
Signed-off-by: Dipen Parmar <dipenp@codeaurora.org>
Fix compilation errors to support gcc-4.8
There is compilation warnning when use '%d" to print a argument
which type is size_t.
In file included from kernel/include/linux/kernel.h:14:0,
from kernel/drivers/coresight/coresight-tmc.c:13:
kernel/drivers/coresight/coresight-tmc.c: In function 'tmc_read':
kernel/include/linux/dynamic_debug.h:64:16: warning:
format '%d' expects argument of type 'int', but argument 5 has type
'size_t' [-Wformat=] error, forbidden warning: dynamic_debug.h:64
Change format '%d' to '%zu' to fix this compilation error
Change-Id: Ia746033b76df7f06e860031ed8d3e249facbe2b5
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
The TMC driver now uses dma_alloc_coherent api to allocate contiguous
memory instead of allocate_contiguous_ebi when configured for ETR. This
eliminates the need for EXPORT_COMPAT support in the TMC driver.
Change-Id: I79550d2ff490c02329e4b860b8aa8816d4890d50
Signed-off-by: Aparna Das <adas@codeaurora.org>
Byte counter overflow is computed based on byte counter value during
byte counter start routine. Two different threads running in parallel
can cause synchronization issue where one thread modifies overflow
based on byte counter value and other thread modifies byte counter
value at the same time. Take respective lock before setting byte
counter value.
Change-Id: I923a34bf918abe4d5e3b0d30ed4887a38db6f427
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Fix error checks for byte counter initialization functions that
are called during probe to avoid null pointer accesses.
CRs-Fixed: 562303
Change-Id: I8f7de6fc4b0658cf649e472d12a00ea5733a8b0a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
During kernel panic, coresight_abort is first called to stop
tracing to the default ETF (circular buffer mode) sink. This is
followed by stopping RTB as part of the panic handler.
Use no log version of readl while dumping ETF in circular buffer
mode to avoid polluting RTB logs with readls responsible for
dumping ETF during kernel panic.
Change-Id: I282516be458c8b38af20cb372803cdff9eb9e8f0
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
The CoreSight TMC driver when configured for ETR requires uncached
memory in RAM to which it routes trace data. In order to allocate
this memory replace existing allocate_contiguous_ebi api with
dma_alloc_coherent api which is the linux standard of allocating
memory.
Change-Id: I59f88009f2abed95fd9b81ea92a7d484b9d6b833
Signed-off-by: Aparna Das <adas@codeaurora.org>
Periodic flushing for ETR to USB uses ETR flush-on-FLUSHIN
external input. Hence, enable flush-on-FLUSHIN by default when
enabling ETR to USB transfers and work around the manual flush
failure by skipping it during ETR to USB disable. Adjust the
periodic flush threshold to the maximum value in order to
reduce the overhead when there is no data to be transferred.
CRs-Fixed: 461885
Change-Id: Ie3a1bbc80e017f187af56fcfdfb52297ba9aa72d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Modify the CoreSight TMC driver for LPAE so that it can support
ETR physical addresses greater than 32 bits when LPAE is enabled.
Change-Id: I6db2c98c4db70262ab45f7ff11fe2a6846259f8a
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
The byte counter feature is enabled only if all the components it relies
on can be succesfully enabled.
Change-Id: I09e9b78c21af66d8cfc7c94d286f5b61adb7f7d6
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
A check for the byte counter interrupt value being such that it
divides the memory reserved into equal size blocks is necessary
only when a non-zero value is specified.
Change-Id: I424c09322f2ee82917359d871f0916b3fb50b0be
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
The CoreSight block can produce an interrupt on transfer of
programmed number of bytes to ETR-memory. Use this feature
to provide an interface to manage the byte counter value and
to collect a continuous data stream from userspace.
Change-Id: Ic00c9b19483be566d0f05005936b4a6ff7ab52f1
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Add support to query CoreSight fuse state and fail the probe
if any of the required fuse(s) are disabled. This enables
a single image with CoreSight drivers compiled in to be run on
both Hardware that has CoreSight functionality disabled via fuse
or left enabled for use.
Change-Id: Ib770cc7f76e2b0644bda9600c92fc3a26823452d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Flush ETR is mapped to TRIGIN[2] and so switch to using it in
order to cause a CTI trigger for TMC-ETR flush during wdog reset.
This avoids any race between TMC-ETR flush to memory and DDR
being put into self-refresh.
CRs-Fixed: 491986
Change-Id: Ia5e643121e040bd9c57c89a4b762b794bc8ddf62
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Modify coresight drivers to perform resource lookup by name. The
coresight drivers now use the reg-names property specified in dt
nodes to lookup for resources.
Change-Id: I986f9687be81706d2424e288b9875c3a93e12d11
Signed-off-by: Aparna Das <adas@codeaurora.org>
This change add the support for activating more than
one usb core in the system in bam to bam mode.
Potentially, we can have up to three usb cores in
the system: HSUSB, HSIC and DWC3.
This change simplify the USB BAM driver design, such that
we can easily define bam to bam paths for more than one usb
core concurrently with flexible peer BAMs configuration.
Change-Id: Ie5acb68f29e30cb6c14d2afd957ac8e21cc7beba
Signed-off-by: Shimrit Malichi <smalichi@codeaurora.org>
Add support for disabling TMC-ETR to USB BAM traffic (which can be
safely done in atomic context) as part of coresight_abort when
TMC-ETR-usb is the current sink.
Change-Id: I13f8989b3807cda89f81144a38be429ddaeb3d76
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Program TMC-ETR to stop on flush by default and dynamically
enable flush on watchdog reset using CTI when TMC-ETR-mem is
enabled and disable flush on watchdog reset when TMC-ETR-mem is
disabled.
This will help flush out pending data when a crash causes a
watchdog reset ensuring that most recent data gets captured in
the TMC-ETR-mem.
The need to dynamically enable and disable flush on watchdog
reset based on current sink state arises from ARM recommendation
to have CTI flush enabled only for one sink at a time.
CRs-Fixed: 455170
Change-Id: If780fe4709098b74860d4b32ab2d151e861cf10d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Program TMC-ETF to stop on flush by default and dynamically
enable flush on watchdog reset using CTI when TMC-ETF (in circular
buffer mode) is enabled and disable flush on watchdog reset when
TMC-ETF (in circular buffer mode) is disabled.
This will help flush out pending data when a crash causes a
watchdog reset ensuring that most recent data gets captured in
the TMC-ETF.
The need to dynamically enable and disable flush on watchdog
reset based on current sink state arises from ARM recommendation
to have CTI flush enabled only for one sink at a time.
Change-Id: Ib1a57122802e335da776c008da20da68e8527b00
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Recommended ETR to usb flush procedure changed. This implements
the new recommended procedure.
CRs-Fixed: 443106
Change-Id: I18a6d457686905cbee75ce081ee4c6b4f6fdc62c
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Joe Maples