Add support to hardware event driver to be able to enable regulators
required for accessing certain hardware event mux registers.
Change-Id: I5fb2b7fa349d2d435b3fad33ce8d971ca00716ee
Signed-off-by: Aparna Das <adas@codeaurora.org>
Instead of configuring gpio on bootup, modify coresight cti
driver to allow configuring gpio when mapping or unmapping
cti trigin and trigout so that the gpio(s) are parked in a
functional state only when the mapping/use case is active
hence avoiding any potential power impact when not used.
Change-Id: I375253843210d3873d443e1da195c86927698167
Signed-off-by: Aparna Das <adas@codeaurora.org>
Ensure CoreSight ETMv4 trace unit is disabled before core is
hotplugged off and subsequently enabled when core is online
to prevent race conditions which may arise between cpu hotplug
and enabling or disabling the trace unit.
Change-Id: I51dce88b22f8266d1bb14bc6c36c63c0f9bca0a6
Signed-off-by: Aparna Das <adas@codeaurora.org>
Setting the CoreSight CTI Gate register enables CTI channel
propagation and clearing this register disables channel
propagation. Current implementation of CTI gate enable and
disable apis is not consistent with this channel propagation
behavior. Fix these api implementaions.
Change-Id: Ibe93f97a785c6c33753c18db4417997f9fbf5af1
Signed-off-by: Aparna Das <adas@codeaurora.org>
Modify the CoreSight CTI driver to save and restore only those cpus
belonging to the cluster for which L2 SCU rail is powered off. Also
prevent access to CTI registers for those CPUs whose L2 rail is
powered down.
Change-Id: I4a7ba242b6897962e5cc414e94afc832c464e164
Signed-off-by: Aparna Das <adas@codeaurora.org>
Some functions may need to know the pipe memory type, whether it
is allocated memory or a private region of internal peripheral
memory. Add an extra parameter to the get_bam2bam_connection_info()
function to return this value based on the preconfigured BAM pipes.
For most functions this info is unneeded. For QDSS, use this value
to determine whether to pass MSM_INTERNAL_MEM to the SPS params
when running on a device that requires it.
Change-Id: Ia9f5630b08a90cb66489a11707919d1855c36ec9
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Modify spinlock usage in CoreSight CTI driver to irqsave and restore
version of spinlock to accomodate calling CTI interrupt acknowledge
api in atomic context.
Change-Id: Id0461aa086a60a0c0a6a9e0fba033e8b9e8a9885
Signed-off-by: Aparna Das <adas@codeaurora.org>
Current code to enable CoreSight NIDnT serial wire debug trace mode
is incorrectly disabling all enabled components even on success. Fix
this to get trace in serial wire debug mode.
Change-Id: I60547b96e7f84e479b1686481aa89295a3f313f0
Signed-off-by: Aparna Das <adas@codeaurora.org>
As the NIDnT hardware sense function use the same detecting gpio
with SD card, if the NIDnT driver directly use this gpio, it will
result in the sdcard can't use any more, need disable this feature
first.
Change-Id: I8743611055113c629b469007701c5b97ca8d411a
Signed-off-by: Pan Fang <fangpan@codeaurora.org>
Currently we read the TMC ETF contents and copy them to DDR until
the end marker is seen. If for some reason HW doesn't provide the
end marker, this can result in memory corruption since the code
will end up in an infinite loop that keeps copying contents
beyond the TMC ETF buffer.
Add an additional check to stop copying TMC ETF contents to DDR
when buffer size is reached even if end marker is not seen due to
a potential HW misbehavior.
CRs-Fixed: 671604
Change-Id: I5a6ec1231371737b8e8c368ded75f5e73ac66095
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
To support acknowledging CTI interrupt from atomic context and/or CTI
save and restore in the absence of hardware clock vote, conditionally
vote for CTI clocks during CoreSight CTI driver probe.
Change-Id: I50d7ceb0381bdaca197ab483d5e2a51246d94b1b
Signed-off-by: Aparna Das <adas@codeaurora.org>
Modify CoreSight TPIU driver to use NIDnT apis to access TLMM
registers instead of TLMM apis used earlier which are now
deprecated. Also modify the TPIU device tree entry to support
this change.
Change-Id: I7ccfe0ac8383160e90219674de8871153cb0621e
Signed-off-by: Aparna Das <adas@codeaurora.org>
Modify CoreSight TPIU driver to disable and release all resources that
have been already successfully enabled in case of an error in enabling
TPIU NIDnT modes.
Change-Id: Idd6ea0c07bf2f7596d79df4940273dd81a56fed2
Signed-off-by: Aparna Das <adas@codeaurora.org>
Add support to save and restore the CTI state for those CTIs which does
not retain state on power collapse.
Change-Id: I5d729d364237d6af12bf9deca5b5173d06be5c13
Signed-off-by: Pan Fang <fangpan@codeaurora.org>
Modify CoreSight TPIU driver to use pinctrl framework only and not
fall back on gpio lib to enable TPIU mictor trace since pinctrl
support is now available for all chipsets that support TPIU mictor
trace.
Change-Id: I44ff39679efe246c0edbe9f68590ba862e5d61df
Signed-off-by: Aparna Das <adas@codeaurora.org>
Add support in the CoreSight CTI driver to be able to create
soft acknowledgement for output triggers.
Change-Id: I56db8dc4390d542ff197b48babef0f4498dcd942
Signed-off-by: Aparna Das <adas@codeaurora.org>
Modify CoreSight CTI driver to allow calling CTI save and restore
from atomic context.
Change-Id: Id8b90c19b5e2d84f4e7a794ccee6974e0de8cf24
Signed-off-by: Aparna Das <adas@codeaurora.org>
The OEM config register bit assignment changed for 8916. Add support
for this new register bit assignment as fuse v2 layout.
Change-Id: I41125fbba4e977eac3300037bddaf80113030475
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Memory dump v2 format uses magic number that is different from
what is used with earlier version. Add support for this change
so that the TMC ramdump can be correctly parsed.
Change-Id: Ib7f5478812e59a44c609fc433e8c742fe30488a9
Signed-off-by: Aparna Das <adas@codeaurora.org>
Change flush input signal from pre_ares to flush_etr. For ETF
to be consistent with the usage model for both ETF and ETR.
Remove property reset-flush-race which is a workaround for
MSM8974v1.
Change-Id: I077f5215e75024e484abb3b68d67372ae6ccd154
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Add the Narrow Interface for Debug and Trace mode in the msm8916
platform which will provides nidnt hardware sensing to debug the
device online.
Change-Id: Ia169c805ea5ebe28ac483bff448e9495edb43811
Signed-off-by: Pan Fang <fangpan@codeaurora.org>
Add support for resetting ETM parameters by default on bootup
which can otherwise be done using sysfs.
Change-Id: I098274a44dd9150ccbf3afd88654eb0a7eb74809
Signed-off-by: Aparna Das <adas@codeaurora.org>
Add support to allow enabling remote processor etm tracing on boot by
default so users don't have to enable it explicitly from sysfs.
Change-Id: I7f719d0b5a504a35cba503c60a7d5d9f8434b309
Signed-off-by: Aparna Das <adas@codeaurora.org>
Enable CoreSight CTI clocks before CTI driver accesseses CTI registers
and disable them right after since these clocks are not required to be
on otherwise.
Change-Id: I23ec911b9471bbce2e91c38a1d049ca142a63aee
Signed-off-by: Aparna Das <adas@codeaurora.org>
Byte counter interrupt feature provides an interface to set byte counter
value and collect continuous trace data stream from userspace. Add support
to read this trace data stream when scatter gather feature is enabled for
TMC ETR configuration.
Change-Id: Ic755b7ae14b4bf13f7f28897ec8827476366eaf7
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Add driver support to enable scatter-gather feature with TMC configuration.
Scatter gather option for ETR DDR mode supports the use of a table of
locations of 4K blocks of physical memory. Since this memory is not
necessarily contiguous, user can increase the trace buffer size as long as
DDR memory is available.
Default memory option is "contig" for TMC ETR DDR configuration. User can
enable scatter gather feature dynamically.
Change-Id: I74136fb86fe751aa33607d3922dce5d572f0a4a2
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Based on sg-enable DT entry, enable scatter gather feature
for TMC ETR configuration. Scatter gather feature is not supported
on all targets. sg-enable entry will help to enable this feature
only on those targets which supports this feature.
Change-Id: I66fe50c653ad9646104b9dc0d77a0fa6f82503dd
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Add device attribute for memory type option with TMC ETR DDR configuration.
This is in preparation for scatter gather feature with TMC ETR
configuration.
Change-Id: If72078f89442e9c58e09392fbced362126dd15e7
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Add client support to register with the memory dump v2 driver to
take advantage of the new enhanced memory dump format.
Change-Id: I8b05d92b3e9f4d1dcaa6dffec8fe05401d72a7ee
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
General cleanup to avoid global name space clashes. This is in
preparation for the memory dump v2 driver.
Change-Id: I884ff3a06c74166dc0cd9004085ab9b43646ef6a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for Embedded Trace Macrocell v4 trace architecture
which is required for instruction trace on ARMv8 arctitecture.
Change-Id: Iff24690e3161eb12d6f0e09af0c45f9739c7ca66
Signed-off-by: Aparna Das <adas@codeaurora.org>
When byte counter feature is enabled, if the rate at which we receive IRQs
is so high that userspace is unable to read the data fast enough, we
throw byte counter overflow error message. However these messages can cause
log spew resulting in watchdog bark/bite. Limit byte counter overflow
message spew by using rate limited function.
Change-Id: I714323893330368965f70a137aaef7ef7cd4029d
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Use pin control framework to configure pin resources for
obtaining TPIU trace via mictor instead of GPIO lib
implementations used earlier. Modify the CoreSight TPIU driver
to implement this change.
Change-Id: Ifc565994214ee7c4f7abb97b4222352becfdf2b4
Signed-off-by: Aparna Das <adas@codeaurora.org>
Change the bam handle data type from u32 to
unsigned long to match sps connect source
and destination.
Change-Id: I55ce477a40e4ab3d1306f8afd1acf491c22874e9
Signed-off-by: Sujeet Kumar <ksujeet@codeaurora.org>
Add support for CoreSight QPDI driver which provides
controlled access to PMIC Debug Interface.
Change-Id: Ia2e6cc4e276923b55f34046a6a422e7533768e72
Signed-off-by: Aparna Das <adas@codeaurora.org>
Dynamically allocate ETR DDR memory so that user can specify
trace buffer size at runtime.
Change-Id: I081b017fa147d7c87789cc504cd9b61b7365c79f
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
As part of moving the headers from mach directory
to a common location compilation issues are arising.
Make the changes which are relevant for USB with
its own header files and also dependent header
files.
Change-Id: Ieef7d04ffdfda249f434e0676fec6da8d8b9cf2c
Signed-off-by: Sujeet Kumar <ksujeet@codeaurora.org>
We call coresight_abort() early in panic pathway to avoid trace buffer
getting cluttered with uninteresting messages; however sometimes it tends
to loose important info such as kernel sending notification to all
peripheral subsystems since it happens after aborting of CoreSight trace.
Add trace event to abort tracing late in kernel panic.
trace_event_kernel_panic and trace_event_kernel_panic_late are mutually
exclusive and can be control using module parameter. With this change user
will be able to choose whether to abort CoreSight trace early or late on
kernel panic.
Change-Id: I84cc299823d929fdf8129c9c728282b32391b7c1
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Add trace event to control aborting CoreSight trace
dynamically based on module parameter. This will help
user to enable/disable coresight_abort on kernel panic.
Also moved CREATE_TRACE_POINTS to panic.c from fault.c
since panic.c is common and shared between 32 and 64
bit platforms.
Change-Id: I51e4049b07adeca571b1a98cd90ff5f307d1d794
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Add device attribute to control ETR DDR memory size dynamically
for TMC configuration. This will help users to specify DDR trace
buffer size at runtime.
Change-Id: Ie1edef7f972435193c96dafb8a94fd6cce97ce6c
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Allow configuring CoreSight funnels required for remote processor ETM
tracing even if QMI server is not available to handle QMI client
requests. This allows enabling ETM trace via other alternatives and
use CoreSight drivers to collect trace data.
Change-Id: I43ba5ba5050af23877ddc53694418c35356bae4f
Signed-off-by: Aparna Das <adas@codeaurora.org>
Architectural changes in the ARM Linux kernel tree mandate
the eventual removal of the mach-* directories. Move the
memory dump driver to drivers/soc/qcom and the memory dump header
to include/soc/qcom to support that removal.
Change-Id: If04f6a4fcd30c864321ac0ff8c6691fc20707cc1
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Signed-off-by: Aparna Das <adas@codeaurora.org>
Remove the sps header file from older location as sps
driver and clients need to use new header file from
new location include/linux.
Resolve the warnings/errors from client drivers due to
new sps header changes.
Change-Id: I1cdb87756abf3425a9bb5d8bf89cd1aa03a01716
Signed-off-by: Dipen Parmar <dipenp@codeaurora.org>
Fix compilation errors to support gcc-4.8
There is compilation warnning when use '%d" to print a argument
which type is size_t.
In file included from kernel/include/linux/kernel.h:14:0,
from kernel/drivers/coresight/coresight-tmc.c:13:
kernel/drivers/coresight/coresight-tmc.c: In function 'tmc_read':
kernel/include/linux/dynamic_debug.h:64:16: warning:
format '%d' expects argument of type 'int', but argument 5 has type
'size_t' [-Wformat=] error, forbidden warning: dynamic_debug.h:64
Change format '%d' to '%zu' to fix this compilation error
Change-Id: Ia746033b76df7f06e860031ed8d3e249facbe2b5
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
The TMC driver now uses dma_alloc_coherent api to allocate contiguous
memory instead of allocate_contiguous_ebi when configured for ETR. This
eliminates the need for EXPORT_COMPAT support in the TMC driver.
Change-Id: I79550d2ff490c02329e4b860b8aa8816d4890d50
Signed-off-by: Aparna Das <adas@codeaurora.org>
Upstream prefers existing drivers be converted to support multiplatform
kernels. This requires drivers to be located in directories that
contain generic functionality instead of specific mach directories.
Move the socinfo driver into drivers/soc/qcom and update the initcall
levels to satisfy dependencies.
Change-Id: If195cd793d84867d371f25136a88f2a7ce239500
Signed-off-by: Xiaocheng Li <lix@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Add QMI messaging support to communicate with remote processors to
enable or disable ETM on remote processors.
Change-Id: I7018492284f1e5816302189f8c4f918b3ab79a64
Signed-off-by: Aparna Das <adas@codeaurora.org>
Byte counter overflow is computed based on byte counter value during
byte counter start routine. Two different threads running in parallel
can cause synchronization issue where one thread modifies overflow
based on byte counter value and other thread modifies byte counter
value at the same time. Take respective lock before setting byte
counter value.
Change-Id: I923a34bf918abe4d5e3b0d30ed4887a38db6f427
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
This change removes source files from the kernel tree that
were not being used during make. The list of used files
was generated using an annotated make log and was then
compared with new files added since the public release of
kernel version 3.10.00. New files which were added but
not used have been removed from the tree.
A diff was also run to determine the list of files that had
been modified since the release of kernel version 3.10.00.
These files were then scrubbed based on the current kernel
configuration, removing invalid and unused conditionals.
Some files which support planned functionality or are
useful in debugging have been excluded from this reap.
Change-Id: Ia44a224d3cea7bc78dd45e8a8279860d35d4b008
Signed-off-by: Ian Maund <imaund@codeaurora.org>
Rearrange show_trigin and show_trigout function locations to be
consistent with other CoreSight drivers.
Change-Id: Ic877155e49aa9379ba98e8473812b7f0359e8024
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for cti enable and disable functions to allow use
cases that require the ability to control the trigger outputs
independent of the trigger mapping and generation configuration.
Change-Id: Id94809be629bb3939a67e8f6711733810aeb1f37
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for setting and clearing triggers to allow use cases
that require software based trigger setting and clearing
functionality.
Change-Id: I826b238f2cb1050394134030bd0810bbcdeb2662
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for pulse triggering to allow uses cases that require
software based pulse trigger generation.
Change-Id: I1ce8fd40cfd0622364c101f9d9bc8aa4540b0344
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Split cti_verify_bounds into cti_verify_trigger_bound and
cti_verify_channel_bound so that they can be used individually
when required.
Change-Id: Ic1cd6802b0f5f0e7d9d31da73b0817d8f1909c3d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add trace event to abort tracing for unhandled aborts such as
data abort and prefetch abort. A common event 'trace_unhandled_abort'
is shared for all unhandled aborts.
Change-Id: I6da9b30c74be48252402188a6f9a7703d21d6276
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
The coresight event module helps abort tracing on user fault
and undefined instruction exceptions. Add module parameter to
control it dynamically.
Change-Id: Iecaa144b99e3786c8c8f570f989f747be12c4fdc
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
If gpio entries are not present in dt file, the resource query
function returns negative value for gpio count. Currently data
type for gpio count is unsigned int which wraps around and gives
positive result for negative value that causes failure while
probing the driver. Modify gpio count data type to integer and
check if it is positive before using it.
Change-Id: I1596f3d1090f5caa70735c66e10f82914ac7ab26
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Modify function names and messages to be consistent with other
modules. Modify function names starting with control_* to
event_*, abort_control_tracing to event_trace_user_fault and
abort_tracing_undef_instr to event_trace_undef_instr.
Change-Id: Ic6101dc8024b8d10713c162ea93e268ba59eaf8a
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Fix error checks for byte counter initialization functions that
are called during probe to avoid null pointer accesses.
CRs-Fixed: 562303
Change-Id: I8f7de6fc4b0658cf649e472d12a00ea5733a8b0a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support to switch between various Narrow Interface for Debug and
Trace (NIDnT) modes namely Serial Wire Debug, UART and Trace modes
through SD card interface.
Change-Id: I3d263fe7ec623b0d9c81021d79a69ba5b54ad7e0
Signed-off-by: Aparna Das <adas@codeaurora.org>
Currently the remote processors do not have access to CoreSight debug
and trace framework. Add support for configuring the required CoreSight
components to enable ETM tracing on these processors.
Change-Id: I1a2aa6567f26124124cf1c570575836e62519052
Signed-off-by: Aparna Das <adas@codeaurora.org>
Read cti mappings only when cti is enabled to ensure required cti clock
is enabled.
Change-Id: I7500b44a44c058f37497c2226b8e1b097e734b87
Signed-off-by: Aparna Das <adas@codeaurora.org>
Vote for a fixed clock frequency for TPIU output to SD to
workaround trace data corruption issues across XO shutdown.
Change-Id: Iaa7e822899685c3b5d0cc01dea1090e817e9b129
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
The sdc io regulator is configured and enabled when TPIU trace via sdc
is enabled. Disable this regulator when TPIU trace is disabled.
Change-Id: Ib1dfacb1c4977c74b1796f17f763f8abea583171
Signed-off-by: Aparna Das <adas@codeaurora.org>
During kernel panic, coresight_abort is first called to stop
tracing to the default ETF (circular buffer mode) sink. This is
followed by stopping RTB as part of the panic handler.
Use no log version of readl while dumping ETF in circular buffer
mode to avoid polluting RTB logs with readls responsible for
dumping ETF during kernel panic.
Change-Id: I282516be458c8b38af20cb372803cdff9eb9e8f0
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
The CoreSight TMC driver when configured for ETR requires uncached
memory in RAM to which it routes trace data. In order to allocate
this memory replace existing allocate_contiguous_ebi api with
dma_alloc_coherent api which is the linux standard of allocating
memory.
Change-Id: I59f88009f2abed95fd9b81ea92a7d484b9d6b833
Signed-off-by: Aparna Das <adas@codeaurora.org>
Periodic flushing for ETR to USB uses ETR flush-on-FLUSHIN
external input. Hence, enable flush-on-FLUSHIN by default when
enabling ETR to USB transfers and work around the manual flush
failure by skipping it during ETR to USB disable. Adjust the
periodic flush threshold to the maximum value in order to
reduce the overhead when there is no data to be transferred.
CRs-Fixed: 461885
Change-Id: Ie3a1bbc80e017f187af56fcfdfb52297ba9aa72d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Modify the CoreSight TMC driver for LPAE so that it can support
ETR physical addresses greater than 32 bits when LPAE is enabled.
Change-Id: I6db2c98c4db70262ab45f7ff11fe2a6846259f8a
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Add support to reset each CoreSight cti device through sysfs. This
disables all cross triggering functionality on cti device by
unmapping all mapped cti trigins and cti trigouts and disabling the
cti device.
Change-Id: I4d1f48ad63e1317c893471e1818cd529dd2b002b
Signed-off-by: Aparna Das <adas@codeaurora.org>
The byte counter feature is enabled only if all the components it relies
on can be succesfully enabled.
Change-Id: I09e9b78c21af66d8cfc7c94d286f5b61adb7f7d6
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
For trace via sdc the sdc io regulator needs to be configured and enabled.
Add support for this in CoreSight driver instead of depending upon the
configured values of sdc io regulator on bootup.
Change-Id: I65f341c1dde58ee5e66372bcfb11393fc33bef54
Signed-off-by: Aparna Das <adas@codeaurora.org>
A check for the byte counter interrupt value being such that it
divides the memory reserved into equal size blocks is necessary
only when a non-zero value is specified.
Change-Id: I424c09322f2ee82917359d871f0916b3fb50b0be
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Modify the hardware events driver so that it can handle the hardware event
mux control register addresses being greater than 32 bits.
Change-Id: Id41ce183fa946b14590947f21fbcea361393543f
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Add support to show the CTI channels mapped onto CTI trigger inputs
and CTI trigger outputs via sysfs for each CTI block.
Change-Id: Ib105651f621516dc2055e72c371780cb4497e43a
Signed-off-by: Aparna Das <adas@codeaurora.org>
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