Vote for a fixed clock frequency for TPIU output to SD to
workaround trace data corruption issues across XO shutdown.
Change-Id: Iaa7e822899685c3b5d0cc01dea1090e817e9b129
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
The factor field was introduced for QDSS clocks to set a rate of
0, 1, 2. The rate for other RPM clocks is set in Hz. The factor
would determine the divisor applied to a rate before sending it
over to the RPM. In order to remove this extra complexity (factor
field), the QDSS driver is made to set rates of 0, 1000, 2000.
Change-Id: I722c32e7c66e16b62d4cf31eb865a80b4a7f3922
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Change CONFIG_MSM_QDSS to granular CORESIGHT configs covering
various CoreSight drivers. This better represents the CoreSight
device topology and allows more flexibility in choosing the
drivers required for a particular platform or chip.
Change-Id: I5ae44442c24c88673f2045ad24dc89e4d86d23cb
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
MSM9625 implements ETM based on ETM version 3.5.
As such the 9625 ETM registers need some additonal configuration
for ETM to be functional. They also have some extra registers which
need to be configured properly while some registers currently being
configured by the driver are absent on 9625. Additonally, the ETMv3.5
can be configured to support data tracing, support for which is
not present in the existing ETM driver.
Change-Id: Ic3e61d0d1abf371653a398a28111b308747a7b6f
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Move debug arch defines to jtag.c since they aren't used anywhere else.
Also rename ARM_DEBUG_ARCH_V7_1 to ARM_DEBUG_ARCH_V7p1 to avoid clashes
with similar define in hw_breakpoint.h that is enabled when hardware
breakpoints are enabled.
Change-Id: I5f4b24b7aec50413f97a5b1854e6fadf2e4ab514
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Support for etr to usb trace output using QDSS BAM to USB BAM
transfers.
Change-Id: Ibb6f8d0cf1d9799668cb22ccaa13966139c8dea5
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Provide CoreSight abort debug api to stop the active trace sink
from any context. This is a best effort api that can be used to
abruptly stop and disable the current trace sink from anywhere
in the kernel to avoid tracing and hence polluting the trace data
after the point of interest has been executed.
Change-Id: I34c528d9febec4265088a7267dbcf0e7a1f87fcf
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Switch all CoreSight drivers to start using the new CoreSight core
layer code. Remove obsolete qdss code.
Change-Id: I2d4496aea0ffd918e0bfbf4b4e58ad82ea634a59
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
This allows users to switch between available trace sinks thus
providing user to choose the best switch for the debug use case.
Change-Id: I0c90396010cfcd9f3ab9d3c6d4c1cc7230632c42
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Complete the rename by changing cs to coresight for variables,
functions and constants.
Change-Id: I506d5872e5c09f201c4f3674d7722d36eca26921
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Since cs is not a well known acronym for CoreSight, rename
directory and files from cs to coresight.
Change-Id: I5f9b12794b80b1c01c9ce0621d53ee6be408a361
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Pratik Patel