The SDHCI reset for data is getting stuck on some of sdhci-msm
controllers. The SDHCI reset usually waits for any pending transfers
on the bus before proceeding with the controller reset. But in the
failure cases, the data transfer seems to be stuck on the bus and
thus preventing the controller from being reset. The workaround is
to force the controller to be reset under such scenarios.
This seems to be helping the controller to return back to good state
at least for the next commands following the failure.
Change-Id: I6135fc167241e3f5c995fa6c1936d355e64cedaa
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
This reverts commit bdc10e75a8.
Reverting all pm_qos common framework changes and their
dependencies.
Change-Id: I7db14865fbd2189570a4dd767775a87d5ef7ad7e
CRs-Fixed: 811532
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
This reverts commit 03e5732d02.
Reverting all pm_qos common framework changes and their
dependencies.
CRs-Fixed: 811532
Change-Id: I4cb47a5a0926676dfb1d5c559250529913726026
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Add support for multiple configurations of setting pm_qos
and have all pm_qos handled from the sdhci-msm driver.
This is used in order to support different hardware
architectures (cpu-to-cluster mapping), different pm_qos
requirements for read/write accesses or to compensate for
different scheduler schemes.
Change-Id: Iade1ec6058e56a7cc81322c2d997df76b7e760a6
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
In order to boost mmc performance on various platforms,
add support for configuring whether set_wake_up_idle()
should be called on the mmc queue thread (mmcqd).
The decision will be set in each individual platform's
dts file.
CRs-Fixed: 787554
Change-Id: I3989d3f5b8228785e6d3bc49c7eb01ebf2fa2f38
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Performance of the workload largely depends on the pm qos votes.
Dynamically identify the core in which the current task is running
and apply the pm qos votes to the cluster that this core belongs to.
This ensures that the performance of the workload is not impacted and
also improves the power efficiency of the system.
Change-Id: I4d7fc5250e73b945fa2cfef63e2be18602233f53
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This reverts commit cd9ba68520.
The original change prevented cpu power collapse.
Change-Id: I9e0d0c2ff71423f9b7bec1f23d96d2340f32c4b7
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Add support for multiple configurations of setting pm_qos
and have all pm_qos handled from the sdhci-msm driver.
This is used in order to support different hardware
architectures (cpu-to-cluster mapping), different pm_qos
requirements for read/write accesses or to compensate for
different scheduler schemes.
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Change-Id: I1770ec7dcb35000b64faff0592dd6d81ca2b265c
This change adds a read-modify-write logic to BKOPS feature enable.
It is required in order to avoid overriding other fields defined
in BKOPS_EN register.
Change-Id: I689f5cd14d9ec1bb881f503a0418026a59e6c197
Signed-off-by: Talel Shenhar <tatias@codeaurora.org>
Currently there was only 1 cpu_dma_latency value which
we pass from DT for pm_qos due to which certain I/O use
cases have power/performance impact.
This patch adds support for dynamic Qos using clk scaling.
Using clk_scaling algo we dynamically decide which Qos value
to request for (i.e. Performance/Init/Power_save_mode).
Pass cpu-dma-latency table with 3 values from DT, which can
be used by sdhci layer to update pm_qos dynamically.
This patch also has backward compatibility with platforms that
does not support dynamic Qos and only pass 1 value from DT.
3 values in DT for following states of sdhci (for dynamic Qos)
1. SDHCI_PERFORMANCE_MODE -- least cpu_dma_latency
2. SDHCI_PERFORMANCE_MODE_INIT -- avg val
3. SDHCI_POWER_SAVE_MODE -- higher then avg.
may get updated with default val
based on sdhci_[enable/disable]
Change-Id: Ibce1681e9087c944a827bedb4bf406701b8ff959
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Include one more state of MMC_LOAD_INIT when resume (which
calls for mmc clk init algorithm) is called
to notify sdhci with SDHCI_PERMORMANCE_MODE_INIT.
Change-Id: I80661d7c9a927ed16925c0b9c00ac7abec608cee
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Rate limit sdhci_dumpregs() prints to avoid unnecessary
and exessive logging which can sometimes lead to watchdog
timeouts (especially due to bad cards).
Change-Id: Ib6be6d563e47c2d2e9e1b6b0410c2c45712a9b17
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This reverts commit 3ec1ed2a8d.
The original 10ms delay is enough to reach power on from power
up. Increase delay is workaround to resovle resume Re-init
retries time out error. The root cause is additional QDSD block
would impact SD fucntionality as they are multiplex with SD
interface. If cd-gpio is HW floating and has a pulse, QDSD 100ms
search process would be triggerred is prior to SD block and SD
interface work as QDSD instead of SD.
The fix is merged, so revert the workaround.
Change-Id: I647be754de4a6a13678cbb1456a9db88c2714f94
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
This change fixes value for SDHCI_QUIRK2_IGN_DATA_END_BIT_ERROR.
As a result of a06fbc9666 wrong value
used.
CRs-fixed: 734310
Change-Id: I3f1ffad1deeb3cba2abbc8e38b4a8c168a65cf22
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Some SDHCi controller implementations did not require alignment
for ADMA buffers. When SDHCI_QUIRK2_ADMA_SKIP_DATA_ALIGNMENT defined,
the logic that fixes scatter gather list buffers is skipped.
CRs-fixed: 719302
Change-Id: I822b394a0ae4f9b8a132c13831c0cdf78684cb36
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Add a capability to selectively increase the delay between
power_up and power_on. This delay was arrived at after performing
a series of experiments to find the minimum value. It is required
in some scenarios to avoid command timeouts during resume.
Change-Id: I857e740aa20a33e08515d054e5c9bf128db229c6
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
With some devices, SD card could not support hotplug as there is
no cd-gpio, and also could not use polling way due to power
comsumption. So add nonhotplug to meet such requirement and when
SD card lost or removed manually, device will not crash until
next reboot process to detect SD card.
Change-Id: Ie8ea8ec57015f36689a119249003eeaa48391393
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
Use the correct power class field from the extended CSD register
for HS400 mode as defined in the eMMC5.0 specification.
CRs-fixed: 690341
Change-Id: Ie10e35941fd3c6ee49c686f721bf5af6fcd74862
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Enabling cache in micron devices with manufacturer ID 0xFE
is resulting in data corruption issues during power-off tests.
CRs-fixed: 654661
Change-Id: Ifcdecb26c4c75b055a128a8d9b883fc028521930
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
eMMC and SD card specifications restrict the usage of a class of
commands while commands in other class are in progress. For example,
during erase operations the SD/eMMC spec. allows only CMD35, CMD36,
CMD38. If clock scaling is enabled and decide to scale up the clocks
it may be possible that CMD19/21 tuning commands are sent in between
erase commands, which is illegal as per specification.
Fix such illegal transactions to the card and also make clock scaling
statistics accountable only for read/write commands instead of time
consuming commands, like CMD38 erase, where transactions are independent
of bus frequency.
Change-Id: Iffba175787837e7f95bde8970f19d0f0f9d7d67d
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
This change prevents enabling cache during card init for specific
Kingstone card.
This change is workaround the problem of long timeouts for cache
operations.
Change-Id: I6be53a408c7d6422556585d4ea2f9b1c487563e0
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
As of now we ignore CRC/INDEX command failures to tuning command
and still wait for data from card but in case the card did not
receive the command, it won't send the data. This is causing
software request timeout for tuning commands. Hence, software
must not ignore such cmd errors for tuning commands but end the
request immediately after resetting the controller for both CMD
and DATA. Also, wait for 146 MCLK cycles for card to send out the
data and thus to move to transfer state. Its corresponding phase must
also be considered as bad phase.
CRs-fixed: 625855
Change-Id: Ic8462dd9c67e4f18a3ce73d972591772be8c6d10
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Get the various drive types other than the default supported
by the card.
Change-Id: I122971e4fb4a3ab98f0078ceafca3380e9c0e2d1
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
This change prevents enabling cache during card init for Hynix cards.
This change is workaround the problem of Hynix cards behavior for
adb reboot flow, when as a result of power cycle with cache enabled,
ext4 journal get aborted, because of meta data corruption.
Change-Id: I3198c940a334c8e5fbc3e68e0fea638e76467a75
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Add a quirk to increase the data-timeout value for Hynix eMMC
cards only. This value is fixed to a maximum of 4 seconds.
Change-Id: I4bca6cbc877b323b29a3f7f5923d0708c48adf2c
CRs-fixed: 587284
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Fix buffer overflow while caching the mmc ext_csd content.
Also, to avoid duplicate allocation keep the allocated ext_csd
till the card is removed.
CRs-Fixed: 583929
Change-Id: I5d69e37f6fd1f5249479d454c353be050df40b6d
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
This patch adds clock scaling support to HS400 cards.
Scaling down to 52MHz from HS400 involves:
- switching the bus-speed mode to HS at 52MHz
Scaling up to HS400 would require all of the initialization
process upto HS400 mode selection.
Change-Id: I8196d6666bcc0ef327659253df53a17792fa51f7
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
There is currently no mechanism to disable the runtime-pm
of eMMC/SD card. This patch adds the mechanism to disable
runtime-pm of eMMC/SD if MMC_CAP2_CORE_RUNTIME_PM is not
defined.
It sets the platform, class and card device as RPM_ACTIVE
irrespective of the capability but doesn't enable it.
The card is never runtime-suspended and hence the
corresponding mmc_host and platform device are not
runtime-suspended as well.
A capability MMC_CAP2_CORE_PM is used to select the use
of core power-management framework.
CRs-Fixed: 490021
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Change-Id: I394a81a889ab7d4f0f0e6fe4b932630e30fc16c9
There is race between sdhci_tasklet_finish()
and sdhci_stop_request(): when the request is finished before
stop flow called, error returned.
Change-Id: Iac43e6af2498bc75bc8cc959c680a92f9dd5ee7a
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
This change involves configuring the ADMA2 in 64-bit mode
based on the controller capabilities and setting up the
64-bit descriptor table so that driver can handle physical
addresses greater than 32-bits when LPAE is enabled.
Change-Id: I070d81212c180cbf23a041ff218106add513c47d
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The SD3.0 voltage switch sequence to 1.8v would involve stopping the
SDCLK before changing the voltage level and with recent changes in 3.10
kernel, the peripheral clocks are also getting disabled instead of
just stopping the clock to the card. This patch makes sure this doesn't
happen by marking the flag card_clock_off in struct mmc_host before
starting the voltage switch sequence and checking it in host controller
driver.
Change-Id: If62378ba1dd369e69524365a4421d57317c22ca2
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
As per specification, auto cmd error status register is valid only
when auto cmd error bit is set in Error interrupt status register.
CRs-fixed: 515513
Change-Id: Id1013e1705d8efdba0171dcad14f783607d38ef3
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Certain Hynix eMMC 4.41 cards might get broken when HPI feature is used
and hence this patch disables the HPI feature for such buggy cards.
As some of the other features like BKOPs/Cache/Sanitize are dependent on
HPI feature, those features would also get disabled if HPI is disabled.
Change-Id: I6a638ce089cbd977122e47aecb721bc3f0adf7b0
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
HS400 bus speed mode also requires tuning to be performed as done in
HS200 mode. Add the capability in host layer to perform tuning for
HS400 too.
Change-Id: I4508739dd76b1aca79f0c975fb31010c6f8ba9df
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
HS400 is a new bus speed mode introduced in eMMC5.0 specification. This
patch adds the capability in mmc core to switch to HS400 mode when both
the host and the card supports it.
Change-Id: I53ee4982eae9e5cfccafe065b532d4a2f7225d17
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The bus speed selection code in mmc_card_init() is convoluted, refactor
the code to simplify this and make it simpler for adding new bus speed
capabilities.
Change-Id: I1ee5365eaad42298a053d0b2d64b87b64bd05c5e
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Some SDHC controllers are unable to handle data end-bit
errors in one bit mode.
This patch adds a quirk to ignore data-end-bit error in
1-bit mode in Qualcomm SDHC controllers.
Change-Id: Ica0f10573d654021449c32197b126e12bb1a3c10
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch initializes wakeup source if the detected card
is a sdio card and enables the wakeup capability.
Platform drivers would have to invoke:
* pm_wakeup_event on this card device to signal a wakeup
* corresponding pm_relax have to be invoked
Change-Id: Ic8d5c98073e8ed3f676eb42fc0ce1f13a11cb40f
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Some controllers can gate the clock to save power
even for SDIO cards. In such cases, an asynchronous
interrupt mechanism is used to receive interrupts
even when clocks are off.
This patch wakes up the sdio thread if interrupts
were received when clocks were off.
Change-Id: Ifcfafad251dedc992637596b6bb9349cfbca5d8b
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Provide sysfs tunables to defer PM QoS vote of default value so that
back-to-back requests wouldn't suffer from latencies caused by CPU
power collapse transition states.
Change-Id: I7180c68c1f13240faa5f432335d72e7f6b198183
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
PM QoS vote of default value mean that the CPU is allowed to move
into deepest low power mode whenever possible. Currently, if there
are back-to-back MMC requests, with a short delay, the PM QoS vote
to default value is done immediately which cause the immediate
request to have high latency as the CPU might have idle'd and moved
to deepest low power mode. To avoid this defer the PM QoS vote till
a defined timeout (pm_qos_timeout_us), so that back-to-back requests
may not suffer from additional latencies.
In addition, if the load on MMC is low, the additional latency may be
sustainable. Hence, aggressively release the vote in order to achieve
additional power savings.
CRs-Fixed: 501712
Change-Id: I82166b0ce9416eb0d519f7da26e5a96956093cb2
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
When the card is removed in mmc_sd_detect(), the card status is
marked as runtime suspended and this asynchronously triggers
runtime suspend of it's parent mmc_host class device. The
mmc_power_off() will be called from runtime suspend handler and
it races with mmc_power_off() within mmc_sd_detect(). Fix this by
acquiring mutex at the host driver when set_ios host operation
is invoked and until it is done.
CRs-fixed: 513141
Change-Id: I4e7afbe966ecbcc2c8bf746fb6cffc64b7cf252e
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
As "bkops_busy" flag is no longer used, remove it from the mmc_command
structure.
Change-Id: Icd405ba4879c5dfc915eba9bf821633fdd87fbb6
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Some of the time consuming operations such as BKOPS, SANITIZE, CACHE
flush/off use the SWITCH command (CMD6) but as these operations don't
have card specification defined timeout for completion, we may see
timeout errors if card doesn't complete the operation within the SW
defined timeout. If SW defined timeout is hit, above operations are
considered to be failed and no real recovery mechanism is implemented
after timeout.
Most of the above operations (BKOPS/SANITIZE/CACHE flush/off) can be
interrupted by sending the HPI (High Priority Interrupt) command to card
if they taking longer than expected. This change adds the base support
which will these operations to be HPIed after timeout.
Change-Id: Ibd9061525756aaae656b1ceeeaed62e04fb80cce
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The driver currently uses fixed timeout value from capabilities
register (bit 5-0) to calculate the timeout which is advertized
as 50MHz. But the driver uses SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK
and controls the base clock (MCLK) directly. So during card
initialization, the frequency would be 400KHz but still timeout
is calculated at 50MHz which is wrong. This patch fixes this by
using the current base clock frequency to calculate the timeout.
The controller internally multiplies the timeout control register
value by 4 with the assumption that driver always uses fixed
timeout clock value from capabilities register. Add a quirk
SDHCI_QUIRK2_DIVIDE_TOUT_BY_4 to avoid this multiplicaiton in
case base clock is used for timeout calculation.
CRs-fixed: 498159
Change-Id: I503fd16132bf17e590239997d6970b9b730d4202
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
At the moment only POWER_OFF_SHORT is sent to the device in case the host
is suspended. This patch adds the support of sending POWER_OFF_LONG
notification in case the device is powered off.
According to device vendors the POWER_OFF_LONG notification will shorten
the initialization time of the eMMC card during next boot up.
Change-Id: I3c6f224398450cf10463cbb316613fd430d1e8d2
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
SDIO 3.0 specification has added the support for asynchronous interrupt
period during which card allows the clock to be gated off. Host needs
to first read the "Support Asynchronous Interrupt" bit in CCCR register
space to check if the card supports the feature or not. If yes and if
the host wants to enable the feature, host needs to write '1' to
"Enable Asynchronous Interrupt" bit in CCCR register space.
This change allows the host controller driver to control whether to enable
the asynchronous interrupt in card or not and if the asynchronous interrupt
is enabled then clock gating feature would be enabled for such cards.
Change-Id: I678cffb63af6a2013640a5eafa6ce9bfad8a51d6
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Dov Levenglick