Add additional parents for the pixel and byte clocks as these can now
switch between those. Also export the sources for the byte and pixel
clocks so that clients can switch between the parents for the relevant
RCGs.
Change-Id: I4e1430778dae4a0b77ecc81836b23b6f8c841197
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Add additional parents for the pixel and byte clocks as these can now
switch between those. Also export the sources for the byte and pixel
clocks so that clients can switch between the parents for the relevant
RCGs.
Change-Id: If2c7fe4f12c6ad5a15f13acf71d6dc296b57b665
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Switch the clock used for the proxy vote (on the PNOC bus) to
be an exclusive voter, so that other votes do not interfere.
Change-Id: I96dd39c7cc64fac69ea2ae8d6bf4a20c0f912527
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
The pnoc_modem_clk had the incorrect md5 hash. Fix it.
Change-Id: I72f773d6f37f1310b24f1db031d38b0850988761
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Add support for shadow DSI PLL implementation for 20nm PLL to handle
dynamic refresh feature.
Change-Id: Ic857aca3ddec6febcf76c0ee73e90964017fd81b
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
The RPM needs to control the mss_cfg_ahb_clk so that CNOC DCD can
be enabled for MSM8992.
Change-Id: Ibead166bf649983dad115f65da87371c180b4a4d
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Introduce bus topology for msmtellurium. This is a representation
of the bus connections in the SOC and allows the bus driver
to setup bandwidth requests from clients for the paths desired.
Change-Id: I73e74df29b45f4d95be630c017117b8992c8003a
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Register using the function of_msm_clock_register that registers a clock
provider with the clock of framework.
Change-Id: I632936ef3f033dd80f93d469d4d921a75ef8e16b
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The gfx driver needs to control the oxili_timer_clk. Add
the support in this change.
Change-Id: I9582c7370f6713828bb010ffb996573f25528657
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
In HW, the rpm clocks reside in the GCC clock controller.
The separation of rpm and gcc clocks is from SW perspective.
However, this separation is not required for the clock
definition. So merge the rpm clocks with the GCC clock
controller.
Change-Id: I0be67855fc67c9d4016cdd8f11c174018855d14d
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
The apss_axi_clk and bimc_apss_axi_clk needs to be gated
on/off during power collapse. Therefore, export their handles
to allow pm driver control them and also make them not always
on clocks.
Change-Id: Ic514aa02888820d87bc516d61193b9caeb52af6f
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
This enables clock reset feature so that clock consumers driver
can call clk_reset.
Change-Id: I7945b4bb740164d7c8b2b8696f67d2a259d3e7f7
Signed-off-by: Arun KS <arunks@codeaurora.org>
Add the ability to switch NoC masters to be in limiter and regulator mode
for the adhoc bus driver. These modes offer differing degrees of
throttling the io traffic from NoC master ports if needed.
Change-Id: If2f868430ebccff1a11aad7d90fa5b352ea2c876
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Big cluster uses HFPLL as clock source.
Little cluster and CCI use SR2PLL as clock source.
Change-Id: Iaf990f0e0f360b3ccac2162584fc286e5b7a54ca
Signed-off-by: Arun KS <arunks@codeaurora.org>
The xo_pil_lpass_clk clock is required to support lpass pil.
Change-Id: Iea86af0de02537e89b6b2384aad0035eb30a14de
Signed-off-by: Rajkumar Raghupathy <raghup@codeaurora.org>
UART3 will be used as a console in FSM9010 targets.
Change-Id: I1f9307cdd76f8541ae3b9c3b579c310542e8f2ba
Acked-by: Kaushik Sikdar <ksikdar@qti.qualcomm.com>
Signed-off-by: Venkatesh Yadav Abbarapu <quicvenkat@codeaurora.org>
This is a control register to generate the QOS signal from XO/4
clock. Add a gate clock to allow enable/disable of the clock.
Change-Id: Ifa63e235bc057bb1746b7cee3a92957631dbc859
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add support for rpm and gcc clocks according to the
hardware and software clock plan for msmtellurium.
Change-Id: I60c17bf6af7fefe7c727cc7bd7007a8e62634882
Signed-off-by: Arun KS <arunks@codeaurora.org>
Create new dts for IPA off-target regression and development, dedicated
to the vp simulation.
Change-Id: I17a9f3ab53c62015330f6dbf56e4547e36ec0c79
Acked-by: Shay Baram <sbaram@qti.qualcomm.com>
Signed-off-by: Gidon Studinski <gidons@codeaurora.org>
Switch the clock used for the proxy vote (on the pnoc bus) to be
an exclusive voter, so that other votes do not interfere.
Change-Id: I168ed65441950536d27f7f9134bd74ed74ad9324
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
There is no ce3 clock on MSM8992 so remove the same.
Change-Id: I9588d28f6595d33a6b0ed69bf7332342d0aea90d
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Introduce a new module to allow clients to set a floor vote on bus clocks
either using an API or via sysfs interface. Clients are still always
recommended to use standard bus scaling APIs , these new APIs are a debug
feature and a meant for debugging system performance issues.
Change-Id: I7688e391413c23d9024a7b525f60c90f317d0847
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Introduce mdm9640 as the official name for msmzirc.
Update msm-tsens and clock-a7 bindings to make checkpatch happy along with
renaming.
Change-Id: I364cc0feab4cf4a1bac03dc08eec0214e09f40f7
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
The cpu clock trees for MSM8994v2 and MSM8992 are very similar. Hence,
add support in the MSM8994 cpu clock driver for MSM8992 and use the
same driver on both.
Change-Id: I04579b4467cafc9b8e4fc70cb8f1f01130f54c16
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
gcc_usb3_phy_pipe_clk's source could be dynamically gated off at any
time. Thus checking branch_clk status bit could result in stuck on/off
warnings. Since the HW design can handle clock input glitch, model
gcc_usb3_phy_pipe_clk as gate clock instead of branch_clk.
Also add gcc_usb3phy_phy_reset for asserting reset bit previously
associated to gcc_usb3_phy_pipe_clk branch.
This patch is simply a carbon copy of commit c32533e8 (clk: qcom:
Change gcc_usb3_phy_pipe_clk to gate_clk) which was for MSM8994.
Change-Id: I04acef3c936d9591f7517677f8ed382269ad74c7
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Bus driver will vote on snoc_mm_msmbus_clk and snoc_mm_msmbus_a_clk for
multimedia clients.
Change-Id: Idc21e7bd031a1295d5126eb4e1db9549cb1af75c
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This file contains all the clocks supported on msmtellurium.
Change-Id: I9db3da8400c22c241aca50c67c713e4a2081323c
Signed-off-by: Arun Ks <arunks@codeaurora.org>
Both qcedev and qcrypto drivers need to vote on the ce
clocks. Therefore, create the voter clocks for them to
allow aggregation of their requests.
In addition, export the phandles for these ce clocks
to allow the clients use them.
Change-Id: I4f026dae7c802a96d10692be1bf74028156fb080
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
Add the prng ahb clock data to allow client control this
clock.
Change-Id: I0a68943ddbf9bcd71c7c792cf726b53b457b6ae9
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
Pushkar Joshi