For controllers that doesn't support card insertion/removal i.e.,
when the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION is defined,
card_event() host op must not rely on present state register
to check the card's status.
CRs-fixed: 644221
Change-Id: Icff6db0d8fe17f01cf751896ae09aee215edc548
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The commit 'e2598c - mmc: sdhci-msm: improve tuning process'
introduces NULL pointer dereference bug for SD 3.0 cards
when all the tuning phases pass. It uses mmc_card_mmc(card)
for checking the card type but card is initialized after
tuning is done for SD card and thus resulting in NULL
pointer dereference issue.
CRs-fixed: 640424
Change-Id: I59a8d5f017243d8391269bc98998bb37fc44f685
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This is aimed to reduce the suspend time of sdhci-msm device.
The suspend of this device would be carried out in a separate
thread and other devices may suspend concurrently. This is
required since the mmc sub-system contributes to the major
chunk of suspend latency.
CRs-fixed: 634333
Change-Id: I7bdead2deacd96aec5201d82b143b07c470b3892
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Enables the asynchronous suspend of card and class device.
This would enable both these devices to suspend in separate
respective threads, thus allowing other devices to suspend
concurrently.
CRs-fixed: 634333
Change-Id: Ic73022ef777b4fae4b1065f92cfa19da51a99634
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
The following commits have been reverted from this merge, as they are
known to introduce new bugs and are currently incompatible with our
audio implementation. Investigation of these commits is ongoing, and
they are expected to be brought in at a later time:
86e6de7 ALSA: compress: fix drain calls blocking other compress functions (v6)
16442d4 ALSA: compress: fix drain calls blocking other compress functions
This merge commit also includes a change in block, necessary for
compilation. Upstream has modified elevator_init_fn to prevent race
conditions, requring updates to row_init_queue and test_init_queue.
* commit 'v3.10.28': (1964 commits)
Linux 3.10.28
ARM: 7938/1: OMAP4/highbank: Flush L2 cache before disabling
drm/i915: Don't grab crtc mutexes in intel_modeset_gem_init()
serial: amba-pl011: use port lock to guard control register access
mm: Make {,set}page_address() static inline if WANT_PAGE_VIRTUAL
md/raid5: Fix possible confusion when multiple write errors occur.
md/raid10: fix two bugs in handling of known-bad-blocks.
md/raid10: fix bug when raid10 recovery fails to recover a block.
md: fix problem when adding device to read-only array with bitmap.
drm/i915: fix DDI PLLs HW state readout code
nilfs2: fix segctor bug that causes file system corruption
thp: fix copy_page_rep GPF by testing is_huge_zero_pmd once only
ftrace/x86: Load ftrace_ops in parameter not the variable holding it
SELinux: Fix possible NULL pointer dereference in selinux_inode_permission()
writeback: Fix data corruption on NFS
hwmon: (coretemp) Fix truncated name of alarm attributes
vfs: In d_path don't call d_dname on a mount point
staging: comedi: adl_pci9111: fix incorrect irq passed to request_irq()
staging: comedi: addi_apci_1032: fix subdevice type/flags bug
mm/memory-failure.c: recheck PageHuge() after hugetlb page migrate successfully
GFS2: Increase i_writecount during gfs2_setattr_chown
perf/x86/amd/ibs: Fix waking up from S3 for AMD family 10h
perf scripting perl: Fix build error on Fedora 12
ARM: 7815/1: kexec: offline non panic CPUs on Kdump panic
Linux 3.10.27
sched: Guarantee new group-entities always have weight
sched: Fix hrtimer_cancel()/rq->lock deadlock
sched: Fix cfs_bandwidth misuse of hrtimer_expires_remaining
sched: Fix race on toggling cfs_bandwidth_used
x86, fpu, amd: Clear exceptions in AMD FXSAVE workaround
netfilter: nf_nat: fix access to uninitialized buffer in IRC NAT helper
SCSI: sd: Reduce buffer size for vpd request
intel_pstate: Add X86_FEATURE_APERFMPERF to cpu match parameters.
mac80211: move "bufferable MMPDU" check to fix AP mode scan
ACPI / Battery: Add a _BIX quirk for NEC LZ750/LS
ACPI / TPM: fix memory leak when walking ACPI namespace
mfd: rtsx_pcr: Disable interrupts before cancelling delayed works
clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock
clk: samsung: exynos4: Correct SRC_MFC register
clk: clk-divider: fix divisor > 255 bug
ahci: add PCI ID for Marvell 88SE9170 SATA controller
parisc: Ensure full cache coherency for kmap/kunmap
drm/nouveau/bios: make jump conditional
ARM: shmobile: mackerel: Fix coherent DMA mask
ARM: shmobile: armadillo: Fix coherent DMA mask
ARM: shmobile: kzm9g: Fix coherent DMA mask
ARM: dts: exynos5250: Fix MDMA0 clock number
ARM: fix "bad mode in ... handler" message for undefined instructions
ARM: fix footbridge clockevent device
net: Loosen constraints for recalculating checksum in skb_segment()
bridge: use spin_lock_bh() in br_multicast_set_hash_max
netpoll: Fix missing TXQ unlock and and OOPS.
net: llc: fix use after free in llc_ui_recvmsg
virtio-net: fix refill races during restore
virtio_net: don't leak memory or block when too many frags
virtio-net: make all RX paths handle errors consistently
virtio_net: fix error handling for mergeable buffers
vlan: Fix header ops passthru when doing TX VLAN offload.
net: rose: restore old recvmsg behavior
rds: prevent dereference of a NULL device
ipv6: always set the new created dst's from in ip6_rt_copy
net: fec: fix potential use after free
hamradio/yam: fix info leak in ioctl
drivers/net/hamradio: Integer overflow in hdlcdrv_ioctl()
net: inet_diag: zero out uninitialized idiag_{src,dst} fields
ip_gre: fix msg_name parsing for recvfrom/recvmsg
net: unix: allow bind to fail on mutex lock
ipv6: fix illegal mac_header comparison on 32bit
netvsc: don't flush peers notifying work during setting mtu
tg3: Initialize REG_BASE_ADDR at PCI config offset 120 to 0
net: unix: allow set_peek_off to fail
net: drop_monitor: fix the value of maxattr
ipv6: don't count addrconf generated routes against gc limit
packet: fix send path when running with proto == 0
virtio: delete napi structures from netdev before releasing memory
macvtap: signal truncated packets
tun: update file current position
macvtap: update file current position
macvtap: Do not double-count received packets
rds: prevent BUG_ON triggered on congestion update to loopback
net: do not pretend FRAGLIST support
IPv6: Fixed support for blackhole and prohibit routes
HID: Revert "Revert "HID: Fix logitech-dj: missing Unifying device issue""
gpio-rcar: R-Car GPIO IRQ share interrupt
clocksource: em_sti: Set cpu_possible_mask to fix SMP broadcast
irqchip: renesas-irqc: Fix irqc_probe error handling
Linux 3.10.26
sh: add EXPORT_SYMBOL(min_low_pfn) and EXPORT_SYMBOL(max_low_pfn) to sh_ksyms_32.c
ext4: fix bigalloc regression
arm64: Use Normal NonCacheable memory for writecombine
arm64: Do not flush the D-cache for anonymous pages
arm64: Avoid cache flushing in flush_dcache_page()
ARM: KVM: arch_timers: zero CNTVOFF upon return to host
ARM: hyp: initialize CNTVOFF to zero
clocksource: arch_timer: use virtual counters
arm64: Remove unused cpu_name ascii in arch/arm64/mm/proc.S
arm64: dts: Reserve the memory used for secondary CPU release address
arm64: check for number of arguments in syscall_get/set_arguments()
arm64: fix possible invalid FPSIMD initialization state
...
Change-Id: Ia0e5d71b536ab49ec3a1179d59238c05bdd03106
Signed-off-by: Ian Maund <imaund@codeaurora.org>
As of now we ignore CRC/INDEX command failures to tuning command
and still wait for data from card but in case the card did not
receive the command, it won't send the data. This is causing
software request timeout for tuning commands. Hence, software
must not ignore such cmd errors for tuning commands but end the
request immediately after resetting the controller for both CMD
and DATA. Also, wait for 146 MCLK cycles for card to send out the
data and thus to move to transfer state. Its corresponding phase must
also be considered as bad phase.
CRs-fixed: 625855
Change-Id: Ic8462dd9c67e4f18a3ce73d972591772be8c6d10
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Moves bus scaling code to architecture independant directory
for platform drivers.
Change-Id: Ie0d5b104882d1534fae262af85e99cc09a56ab04
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
Fix possible NULL pointer dereference within cd-gpio IRQ
handler mmc_gpio_cd_irqt(), which can potentially happen
if the card detect IRQ gets triggered before host->ops
are initialized.
CRs-fixed: 628836
Change-Id: I2f47717d338c5c7f8e7a994c28bb5c30b30286c6
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
When ADMA is disabled the max segments and max req size were not set
properly, set them right to use the driver in PIO mode.
Change-Id: I754c30c017062540335f96480d103f054cc38084
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Commit 6932a01cd (mmc: card: quirk: disable cache for Hynix card)
claims to disable cache because of data corruption issues when cache
it is enabled. In reality, the patch allows enabling of cache during
card initialization but disallow flushing of cache during suspend or
file system sync operations. This is more dangerous than without
the commit. Move the fixups for disabling cache to mmc_fixups so as
to enable the quirk during initialization itself. Also, remove obvious
warnings everytime card is initialized during runtime resume.
Change-Id: I3f71eaccf90ffdea83f418b7c05be68f5d89d227
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
In newer hardware, the tuning process is not able to always
find a reliable phase to use for sampling data. This is mostly
due to hardware. This problem manifests itself as all successful
tuning phases, which means that the phase choosen could be a bad
one but is not identified as such at the time of tuning. So in
order to work around this, rely on optional drive types implemented
by the eMMC card, in addition to the mandatory drive type (50 ohm).
By using drive types supported by the card, when all phases are
sucessful in tuning, change drive type to a different value in the
list of supported drive types and retune. This will continue for all
tuning phases until a valid one is found. After that the drive type
is reset to the default one, if changed.
Change-Id: I348fb30daa43d97c58f83f7e4a22019f94ef4954
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Get the various drive types other than the default supported
by the card.
Change-Id: I122971e4fb4a3ab98f0078ceafca3380e9c0e2d1
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
This is needed for supporting 64-bit kernel.
Change-Id: Id4f60dc15688a6f02f31d77705ad1ef0181a1ce9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
In the current code, if sdhci_check_state returns true a tasklet is
scheduled which doesn't complete the request if host->mrq is NULL,
which is the case, if sdhci is in bad state. This would make the
mmcqd thread wait for completion infinitely.
Hence, complete the request if sdhci_check_state returns true instead
of scheduling the tasklet.
CRs-Fixed: 615537
Change-Id: I8e2950c3999ac3806f9d631c52d86f0dc13b992f
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Fix the following compilation issue when CONFIG_PM_SLEEP is defined and
CONFIG_PM_RUNTIME is not defined -
error: implicit declaration of function 'sdhci_msm_runtime_suspend'
[-Werror=implicit-function-declaration]
return sdhci_msm_runtime_suspend(dev);
^
error: implicit declaration of function 'sdhci_msm_runtime_resume'
[-Werror=implicit-function-declaration]
return sdhci_msm_runtime_resume(dev);
^
cc1: some warnings being treated as errors
make[5]: *** [drivers/mmc/host/sdhci-msm.o] Error 1
Change-Id: Id720f595746888c81c07426aab0c850cbaeccf0c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
In some cases, it is possible that the hardware might trigger
an interrupt just about the same time the software tries to
reset the controller. In such case, the hardware interrupt will
be handled after the current thread release spin lock. This leads
to spurious interrupt handling after the completion of reset.
Change-Id: I75211adee1179b0636a918f5ceb68a072ad02a6c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
commit 66b512eda74d59b17eac04c4da1b38d82059e6c9 upstream.
With some SDIO devices, timeout errors can happen when reading data.
To solve this issue, the DMA transfer has to be activated before sending
the command to the device. This order is incorrect in PDC mode. So we
have to take care if we are using DMA or PDC to know when to send the
MMC command.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit f662ae48ae67dfd42739e65750274fe8de46240a upstream.
Under function mmc_blk_issue_rq, after an MMC discard operation,
the MMC request data structure may be freed in memory. Later in
the same function, the check of req->cmd_flags & MMC_REQ_SPECIAL_MASK
is dangerous and invalid. It causes the MMC host not to be released
when it should.
This patch fixes the issue by marking the special request down before
the discard/flush operation.
Reported by: Harold (SoonYeal) Yang <haroldsy@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
mmc block data can be NULL. Hence, check for NULL before
dereferencing md.
CRs-Fixed: 562259
Change-Id: I0182c216ec73347cdd2ea464f593839fffd242a9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Merge the second phase of support needed for the 8916
target into msm-3.10. This includes a couple hundred upstream
patches for ARM64 support, as well as 8916 specific driver
development.
* origin/tmp-branch: (211 commits)
ARM: dts: msmplutonium: Update the cpu release address
Revert "arm64: Fix memory shareability attribute for ioremap_wc/cache"
clocksource: arch_timer: Do not register arch_sys_counter twice
xtensa: adjust boot parameters address when INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX is selected
sched_clock: Add support for >32 bit sched_clock
sched_clock: Use an hrtimer instead of timer
sched_clock: Use seqcount instead of rolling our own
clocksource: Extract max nsec calculation into separate function
ARM: sched_clock: Load cycle count after epoch stabilizes
sched_clock: Make ARM's sched_clock generic for all architectures
of: move of_get_cpu_node implementation to DT core library
of: introduce common FDT machine related functions
of: Introduce common early_init_dt_scan
mm: allow pgtable_page_ctor() to fail
of: only include prom.h on sparc
mm: introduce helper function mem_init_print_info() to simplify mem_init()
mm: use a dedicated lock to protect totalram_pages and zone->managed_pages
KVM: Move gfn_to_index to x86 specific code
ARM: KVM: move GIC/timer code to a common location
arm64: mm: Fix PMD_SECT_PROT_NONE definition
...
Conflicts:
arch/arm/mach-msm/board-8226.c
arch/arm/mach-msm/board-8610.c
arch/arm64/kernel/asm-offsets.c
arch/arm64/kernel/fpsimd.c
arch/arm64/kernel/setup.c
Change-Id: I289996bc18d8a2782906e7db1171b48e3ee46a73
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
After the last architecture switched to generic hard irqs the config
options HAVE_GENERIC_HARDIRQS & GENERIC_HARDIRQS and the related code
for !CONFIG_GENERIC_HARDIRQS can be removed.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Git-commit: 0244ad004a54e39308d495fee0a2e637f8b5c317
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[imaund@codeaurora.org: resolve merge conflicts]
Signed-off-by: Ian Maund <imaund@codeaurora.org>
In case of illegal buffer passed down by user, return -EFAULT instead
of count.
Change-Id: I2ce2ba5e8d26245fe828e8b6f102c218125bdf3b
Signed-off-by: Lee Susman <lsusman@codeaurora.org>
Merge support needed for the ARM64 8916 target into msm-3.10.
* origin/tmp-b7dbbd5: (289 commits)
arm: add pdev_archdata for dma_mask
thermal: tsens: fix compilation warning
msm: sps: remove sps header file
defconfig: arm64: msm: enable gpio sysfs reporting
arm64: Align CMA sizes to PAGE_SIZE
msm: ipa: add 64-bit support for IPA
defconfig: msm: Enable IPC Router and QMI kernel interface
msm: kgsl: Implement ioctl_rb_issueibcmds for compat
msm: rndis_ipa: add support for 64 bit
msm: ecm_ipa: add support for 64 bit
ARM: dts: msm: Add SPI clocks for QUP1 on plutonium.
ARM: dts: msm: Configure SPI on plutonium QUP1.
msm: ipa: set dma mask of IPA device
msm: ipa: add support for compat_ioctl
msm: ipa: move out of mach tree
arm: dts: msm8916: Change property for CMA regions
arm64: Change type of dma_{alloc,free}_from_contiguous
msm: kgsl: manage active count for perfcounter read compat ioctl
ion: msm: Add custom compat ioctl
ion: Add custom_compat_ioctl
...
Conflicts:
arch/arm/mach-msm/Kconfig
drivers/platform/msm/ipa/teth_bridge.c
Change-Id: I2e5ebfd104d72a91191fef6de33e107399c17938
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
If cpu-dma-latency is not defined in dts files, set it
to 200usec
Change-Id: I27b0357b4d88842a258332250bae66efac3ee5e2
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Remove the sps header file from older location as sps
driver and clients need to use new header file from
new location include/linux.
Resolve the warnings/errors from client drivers due to
new sps header changes.
Change-Id: I1cdb87756abf3425a9bb5d8bf89cd1aa03a01716
Signed-off-by: Dipen Parmar <dipenp@codeaurora.org>
There is a new header file for 64bit platforms.
Change-Id: Iead9ccab1fd0b7249baf670e67872fcffeccf21d
Signed-off-by: Raviv Shvili <rshvili@codeaurora.org>
As a result of following fix: "mmc: core: do not reinsert prepeared
FUA and FLUSH requests in stop flow" REQ_FUA and REQ_FLUSH requests
are not reinserted back into i/o scheduler, but instead started request
execution.
This change will prevent cleaning current request pointer for such
requests.
Change-Id: I25f8706954fb538be62182c87d5fb20354696b7a
CRs-fixed: 600127
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Add support for Linux pin control framework while also supporting
the older TLMM configuration for backward compatibility
CRs-Fixed: 568232
Change-Id: Ib6b8f41fd6ced9aa62c980d7e4a73469603cbc5b
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
This change prevents enabling cache during card init for Hynix cards.
This change is workaround the problem of Hynix cards behavior for
adb reboot flow, when as a result of power cycle with cache enabled,
ext4 journal get aborted, because of meta data corruption.
Change-Id: I3198c940a334c8e5fbc3e68e0fea638e76467a75
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
With commit 0797e5f145 (mmc: core: Fixup signal voltage switch), voltage
switch sequence for UHS-I cards is broken if used with sdhci driver.
The commit expects the SD clock to be disabled when mmc_set_ios() is
issued but sdhci_do_set_ios() re-enables the SD clock for few cycles
after disabling which is a specification violation during voltage
switch sequence. This failure is observed only for a small group of
cards where they ultimately fall-back into high-speed mode even if
UHS-I modes are supported.
Change-Id: Ie275326627a84bfcd4352637a043296c01c175a6
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
During card detection within mmc_rescan(), mmc_rpm_hold() will be called
on host->class_dev before initializing the card and shall be released
after card detection. During card detection, once the card device is
added, MMC block driver probe gets called and in case that probe fails
due to block read/write cmd error, then the block driver marks that card
as removed. Later when mmc_rpm_release() is called within mmc_rescan(),
the runtime suspend of host->class_dev will be invoked immediately. The
commands that are sent during runtime would fail with -ENOMEDIUM and if we
propagate the same to rpm framework, the runtime suspend/resume for this
device will never be invoked even if the card is detected fine later on
during subsequent removal and insertion. Hence, do not report this error to
upper layers.
Change-Id: I9e60e9fb4ebc3d267cedae14aa88021000311427
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
CLK_PWRSAVE bit in vendor specific register gates the output clock to
card automatically if there are no data/cmd operations.
According the SD3.0 voltage switch sequence the host should provide
clock to the card for atleast one millisecond before DAT[3:0] lines
are pulled high by the card. In this case if power save bit is enabled
it might auto-gate clocks even before the card completes voltage
switch sequence.
Fix this by disabling power save operation when the clocks are turned
off and enable only when clock rate is >400KHz i.e., end of initialization.
CRs-Fixed: 589992
Change-Id: If82d6d2e303b8d1189b76712e514f41fe6e2cf8b
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Ensure that MMC/SD card is runtime resumed while enabling or disabling
clock scaling from sysfs. This is needed because the tuning commands
might fail if the card is runtime suspended.
Change-Id: I03767a9ceda2c424f0ce939b8db309d7e81a71da
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
In case if a removable card is hot-plugged when the card and host
are runtime suspended then the mmc_rescan() tries to detect the card
status and removes the bus_ops. During card removal the Linux device
model calls pm_runtime_remove() of the corresponding "card" device,
which not only marks the device as suspended but also notifies the
parent so that it can be suspended if there are no children that are
holding resume. In case if the runtime suspend work of host is scheduled
before bus_ops are marked NULL in mmc_rescan(), the runtime suspend
of host fails with -ENOMEDIUM error. This error makes runtime PM framework
to permanently mark the host device in error and further runtime PM
operations are disallowed even when the card is re-inserted.
CRs-Fixed: 593475
Change-Id: Ie5e09f05ef26098c561b0c64b3954962d9d4c039
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
When mmc context has unblocked from waiting current request because of
urgent request notification coming from block layer, there is prepeared
request. In the case, when the request is REQ_FUA or REQ_FLUSH, the
flow should not reinsert it back to i/o scheduler (since according to
block layer logic flush requests with data should never enter elevator).
Instead this request starts immediately.
Change-Id: Ia78b56c6135dd1a8d75a98fd5b771a5035e5c360
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
MPM hardware acts as an interrupt controller when the apps has gone
to deep sleep states where GIC (the apps main interrupt controller)
has power collapsed. The MPM monitors certain GIC and GPIO lines
while APPS is sleeping and wakesup the apps when a favourable
transition is seen on those monitored lines.
It is an interrupt controller hence move its header to include/irqchip.
Change-Id: I2599784dd91bba73b51ca197e8da69b9c56f78a5
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Initiate a DLL (delay locked loop) retune for the next command,
if the current command fails with a CRC error.
This may help to choose a different phase (delay) if the same
has changed over the elapsed period of time.
CRs-Fixed: 587985
Change-Id: I21f6a5dadb096dd38d41fcf2251fa50b03c8bbb4
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Clock scaling feature would scale up/down the MMC interface clock
frequency based on the load on storage. During clock scale up in HS400
bus speed mode, SW is unncesserily doing the tuning even after HS400
switch is done. This change fixes this bug.
Change-Id: Ica39acc41b14095438a7ccf536c3c7e5792d9c41
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Remove maximum timeout for all cards, since this causes
a long resume time for SD cards. Now only Hynix cards would
have this maximum timeout and this would be decided at the core
layer.
Change-Id: I758f9e5ecf407aba371928a86c313cf69e3cda63
CRs-fixed: 587284
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Add a quirk to increase the data-timeout value for Hynix eMMC
cards only. This value is fixed to a maximum of 4 seconds.
Change-Id: I4bca6cbc877b323b29a3f7f5923d0708c48adf2c
CRs-fixed: 587284
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Architecutural changes in the ARM Linux kernel tree mandate the
eventual removal of the mach-* directories. Move the
mach/clk-provider and mach/clk header to include/linux/clk.
Change-Id: I495f8332bf5d0d09ccfb236c819dea2bacb13542
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
In low memory conditions at runtime, allocation of max_segs may
fail. Retry with a scaled down max_segs until allocation succeeds.
CRs-fixed: 583267
Change-Id: I072724afa44854dacc58654e6329531c1bb11120
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
With SDCC5 the capabilities register is not advertising the
8-bit capability feature (except for 8974 and 8084).
So add the software capabilities for 8-bit slot for rest of
the targets with SDCC5.
Change-Id: I288292f37d77507bf5aaa44bf156496b4df87234
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
Fix compilation issues when CONFIG_PM_SLEEP and CONFIG_PM_RUNTIME
is not defined in kernel.
Change-Id: I74b3f8d335388a0abde707f3e1c5d17f448ac866
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
commit c8760069627ad3b0dbbea170f0c4c58b16e18d3d upstream.
Current MMC driver doesn't handle generic error (bit19 of device
status) in write sequence. As a result, write data gets lost when
generic error occurs. For example, a generic error when updating a
filesystem management information causes a loss of write data and
corrupts the filesystem. In the worst case, the system will never
boot.
This patch includes the following functionality:
1. To enable error checking for the response of CMD12 and CMD13
in write command sequence
2. To retry write sequence when a generic error occurs
Messages are added for v2 to show what occurs.
Signed-off-by: KOBAYASHI Yoshitake <yoshitake.kobayashi@toshiba.co.jp>
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add trace events to capture mmc suspend-resume latencies.
This would be useful to capture latencies for variety
of MMC/SD cards and decide on best possible runtime PM timeout.
Usage -
cd /sys/kernel/debug
echo 1 > tracing/events/mmc/mmc_resume_host/enable
echo 1 > tracing/events/mmc/mmc_suspend_host/enable
cat tracing/trace_pipe
Change-Id: Ic3a73753d55985c1c663cf2972cbed320e0fcfc3
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Fix buffer overflow while caching the mmc ext_csd content.
Also, to avoid duplicate allocation keep the allocated ext_csd
till the card is removed.
CRs-Fixed: 583929
Change-Id: I5d69e37f6fd1f5249479d454c353be050df40b6d
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
commit fbd986cd420d1deeabf1039ec4e74075a5639db5 upstream.
In some cases, a NULL pointer dereference happens because data is NULL when
STATE_END_REQUEST case is reached in atmci_tasklet_func.
Signed-off-by: Rodolfo Giometti <giometti@enneenne.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit c1fa3426aa5c782724c97394303d52228206eda4 upstream.
When a software timeout occurs, the transfer is not stopped. In DMA case,
it causes DMA channel to be stuck because the transfer is still active
causing following transfers to be queued but not computed.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Reported-by: Alexander Morozov <etesial@gmail.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Use sentinels as the path terminator for device match table
in drivers msm_sdcc.c and sdhci-msm.c. Without this, of_dev_lookup()
may run off the end of the array looking for bogus data.
CRs-Fixed: 582113
Change-Id: I069d3e058cea9f1bf74d48e7f7e83465ca981017
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
With SDCC5 the capabilities register is not advertising the
3.0 voltage features (except for 8974 and 8084).
So add the software capabilities for voltage initialization
for rest of the targets with SDCC5.
CRs-Fixed: 568227
Change-Id: Ida53f5ad7249cd0cd8428b4839dfd932b04e31fa
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
The SDHCI host control2 register offset is 0x3E which is not
word aligned and is only 16 bits wide. But we use readl/writel
to read/write to it. Use readw/writew to avoid any alignment
issues.
Change-Id: Ibaa87ce46f2a2dd97f9e1c7979adb38e426acd5b
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
A callback to turn-on the controller clocks is implemented.
This callback would ensure that the pclk and mclk are enabled
but the output clock to the card is disabled.
CRs-Fixed: 567658
Change-Id: Ic97e600a6388fb64f1267a097b201f31d114a1fb
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Currently, the clock to the card is enabled prior to enabling
the power to card. Specification requires that the power be
supplied first and then a delay of 10ms and then clock be
provided to the card.
In this, during MMC_POWER_UP mode, the controller clocks would be
ON and the power would be supplied to the card. In the MMC_POWER_ON
mode, the clocks to the card would be enabled and the rate set.
A callback has been provided to facilitate the enabling of
controller clocks.
CRs-Fixed: 567658
Change-Id: I2d66eae1581b9b136faaba4cafc330aeb6a3f364
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
In mmc_block_test, the debug_fs based read function handlers write to an
arbitrary buffer which is given by any user. We add an access_ok check
to verify that the address pointed by *buffer is not in kernel space.
Only if the buffer is valid, do we continue the read handler.
Change-Id: I35fe9bb70df8de92cb4d3b15c851aa9131a0e8d9
Signed-off-by: Lee Susman <lsusman@codeaurora.org>
According to eMMC specification, there is no upper bound defined on
a flush request and the duration of flush operation is left to card
vendor's implementation. This means that it may take a very long
time to complete.
When eMMC cache is disabled, the card has to flush all the data in its
cache. So this means that for certain cards, the driver is not waiting
long enough for the flush to complete during cache disable operation,
leading to data on the card being corrupted.
This change increases the timeout for cache disable operation, thus
preventing data corruption.
CRs-Fixed: 562350
Change-Id: If68328ab56b50c7596800f07ef92c0ab16a55ec0
Signed-off-by: Maya Erez <merez@codeaurora.org>
Signed-off-by: David Ng <dave@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
During secure discard, the sanitize operation is started
without any timeout value set, which result in a timeout
of 10 seconds applied at the SDHCi driver.
But since the sanitize operation was started after secure
discard was issued, it could take longer than 10 seconds.
So setting a timeout of 30 seconds based on testing done
so far.
CRs-Fixed: 567327
Change-Id: I27e3c9743ca17c151d478b8772649c366a2fd8f3
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Update logging with:
- prefix with module name
- add '\n' in the end
- test_pr_* removed
Change-Id: I465c9809def9d294dcbb3f7cf7f474c189f5fdbf
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Several data-timeout issues were seen, most of which were
due to the card taking a longer time to respond. This patch
increases the timeout of the controller to 0xF i.e. max
possible.
Change-Id: I6739de3eb5d9cccf8e39d9dc4730056782334162
CRs-Fixed: 536832
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
In the MMC card debug_fs the read and write handlers use the strlcat
and sscanf, without checking the pointer given.
Since the pointer is not checked it is possible to write
everywhere (ring 0 or 3).
In order to fix it, an access_ok function is being used to verify
the buffer's pointer supplied by user is valid.
CRs-fixed: 545716
Change-Id: I13ca736337fefe29ff9b0df6a318e7d92240f8b2
Signed-off-by: Raviv Shvili <rshvili@codeaurora.org>
This patch enables the deferred resume support which would
prevent initialization of the card each time the system resumes.
With this change, the resume process would only be initiated if
a request is received.
Following scenario can occur:
1. device runtime suspended, system suspend is triggered
When resumed, the device would not be resumed until a
request is received.
2. device is runtime active, system suspend is triggered
When resumed, the device would be marked as BUS_NEEDS_RESUME
and actual resume would happen, when a request is received.
At this point, the device may also enter runtime-suspend or
system suspend may also occur. In both the cases, since the
device has not been resumed, it won't be suspended again.
However, the platform device would be runtime suspended
and resumed as before.
It can so happen that the card is removed even before a
request is received. In this case the device would be
resumed and card would be removed from core layer and
upper layers would be notified.
In case of SDIO cards, this change would not have any effect
since manual resume would be enabled for devices supporting
a block read/write commands.
CRs-Fixed: 561382
Change-Id: Id39befea109ee24864dfde0898395b972d0a1b3a
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
In case of any error within mmc_blk_alloc_req(), the bitmaps
that keep track of devices are not getting cleared. This may
result in failure to detect a card in case it reaches maximum
devices limitation. Fix it by clearing those bitmaps appropriately.
CRs-fixed: 563264
Change-Id: I0e23c45856355565534146f5fabb957fd4b1d007
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Added checks to check if card is NULL before accessing it.
CRs-Fixed: 548450
Change-Id: Idc005b8420a78b3566164102fbeaa243a8e73c7c
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch adds clock scaling support to HS400 cards.
Scaling down to 52MHz from HS400 involves:
- switching the bus-speed mode to HS at 52MHz
Scaling up to HS400 would require all of the initialization
process upto HS400 mode selection.
Change-Id: I8196d6666bcc0ef327659253df53a17792fa51f7
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
msmsdcc_request_end when called with interrupts disabled inside an
interrupt handler adds an unnecessary 5ms delay on command timeouts,
which impacts system performance. Remove this delay.
Change-Id: I90aec109fe84f7b9f9a9362b5ee2d8d1310833af
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Defining this capability would invoke the suspend/resume
routines defined for mmc_host device by the PM framework.
CRs-Fixed: 490021
Change-Id: I6fde407ed91f0a7249923bb156482378e2bb727c
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
There is currently no mechanism to disable the runtime-pm
of eMMC/SD card. This patch adds the mechanism to disable
runtime-pm of eMMC/SD if MMC_CAP2_CORE_RUNTIME_PM is not
defined.
It sets the platform, class and card device as RPM_ACTIVE
irrespective of the capability but doesn't enable it.
The card is never runtime-suspended and hence the
corresponding mmc_host and platform device are not
runtime-suspended as well.
A capability MMC_CAP2_CORE_PM is used to select the use
of core power-management framework.
CRs-Fixed: 490021
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Change-Id: I394a81a889ab7d4f0f0e6fe4b932630e30fc16c9
The SDCC5 controller and later revisions can handle reset in middle of
an ongoing transfer without the need to disable AHB bus transaction
separately. Disable the workaround for the newer revisions of the core.
Change-Id: I825bff8cccfc3084af9bbbf67a241bb73647872f
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
There are certain cases where the card detect gpio is not handled properly
when broken card detection quirk is used.
Currently the code enables polling irrespective of the presence of card
detect gpio when broken card detect quirk is enabled. Instead only enable
polling when the card detect gpio is missing along with the quirk.
Also when checking for the card detect status, check for the presence or
absence of a valid gpio before assuming that the card is always present.
Change-Id: I178b22031704ff102602271ae4ad16e30f14778f
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
In the MMC card debug_fs the read and write handlers use the strlcat
and sscanf, without checking the pointer given.
Since the pointer is not checked it is possible to write
everywhere (ring 0 or 3).
In order to fix it, an access_ok function is being used to verify
the buffer's pointer supplied by user is valid.
CRs-fixed: 545716
Change-Id: Ia710b6af5a95974fc930ca902e8ff18afa4e17ba
Signed-off-by: Raviv Shvili <rshvili@codeaurora.org>
When mmc_stop_request() has no request to stop, because underlying
host driver reported this, the flow should wait for the mmc done()
callback marking that urgent still pending.
CRs-Fixed: 538117
Change-Id: Ib684949619043882df69f4f1f9c45e28a67a5248
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
There is race between sdhci_tasklet_finish()
and sdhci_stop_request(): when the request is finished before
stop flow called, error returned.
Change-Id: Iac43e6af2498bc75bc8cc959c680a92f9dd5ee7a
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
commit f936f9b67b7f8c2eae01dd303a0e90bd777c4679 upstream.
I'm testing SH-Mobile SDHI driver in DMA mode with a new DMA controller using
'bonnie++' and getting DMA error after which the tmio_mmc_dma.c code falls back
to PIO but all commands time out after that. It turned out that the fallback
code calls tmio_mmc_enable_dma() with RX/TX channels already freed and pointers
to them cleared, so that the function bails out early instead of clearing the
DMA bit in the CTL_DMA_ENABLE register. The regression was introduced by commit
162f43e31c (mmc: tmio: fix a deadlock).
Moving tmio_mmc_enable_dma() calls to the top of the PIO fallback code in
tmio_mmc_start_dma_{rx|tx}() helps.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This reverts commit 1cb3485099.
This is a stable backport from a kernel before v3.10 so it
shouldn't be in 3.10 twice. Nothing is broken if we leave it
though because they're just duplicate entries.
Change-Id: If33c067fbcefbcd5a590ee579e0564c54ca792d6
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
On some eMMC cards cache flush is taking longer than 30 sec timeout
after HPI issued and -EIO reported to the upper layers. This may result
into journaling issues as flush calls are issued by the file system
joulrnaling code.
This change increases flush cache timeout to 90 sec, in case of timeout
occurs, after HPI issued, flush request re-queued to the block layer queue
to execute it later and keep journaling logic valid.
CRs-fixed: 545528
Change-Id: I1e968c07056062fd9c8e14e5bc3e62b3b4b99c64
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Up until now the FLUSH timeout error was not printed and there
was no way to know if the FLUSH completed successfully or not.
Printing the FLUSH failure will help to identify if FS corruption
happened due to this timeout.
Change-Id: I352423c84e2ca698284b90af5837ba96d03919bf
Signed-off-by: Maya Erez <merez@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
The SD cards functionality on QRD devices are failing
with CRC errors when used with higher clock / bus modes.
So reduce the clock speed for SD card slot.
CRs-Fixed: 491789
Change-Id: I24b8bfe44cee4367c22846747f439365d8795d2e
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
On machines that support more than 32-bit address via lpae or 64-bit buses
set the dma mask as 64-bit.
Change-Id: Ida88f3999fd5e7d09ebe73bb3481d3f1f4cf30c2
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
This change involves configuring the ADMA2 in 64-bit mode
based on the controller capabilities and setting up the
64-bit descriptor table so that driver can handle physical
addresses greater than 32-bits when LPAE is enabled.
Change-Id: I070d81212c180cbf23a041ff218106add513c47d
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
During probe disable the HC mode since the reset is done in
SDCC mode. HC mode will get set after the reset is complete
before the rest of the initialization is done.
Change-Id: I1fdc633c218447c15c8caad24e2805e7510088f2
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The SD3.0 voltage switch sequence to 1.8v would involve stopping the
SDCLK before changing the voltage level and with recent changes in 3.10
kernel, the peripheral clocks are also getting disabled instead of
just stopping the clock to the card. This patch makes sure this doesn't
happen by marking the flag card_clock_off in struct mmc_host before
starting the voltage switch sequence and checking it in host controller
driver.
Change-Id: If62378ba1dd369e69524365a4421d57317c22ca2
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This patch whitelists the AR6004 card for clock-gating.
The controller supports asynchronous interrupt functionality
which enables to receive interrupts from the card when clocks
are off. Hence, clocks can be turned off when idle.
This patch whitelists the card, to let the clock-gating
framework gate the clock during idle time.
Change-Id: I651f86e42595cc82f99093c06ee220a1d0ec95a9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch adds the sdio wakeup funtionality in either of the
two methods:
1. If a dedicated mpm interrupt is present in the particular
slot, it is configured to be used as wakeup.
2. If dedicated mpm interrupt is absent for a slot, then
DAT1 line gpio is configured as wakeup.
Change-Id: Ide54f807c12262429011e245de7dcecadcc60f3b
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
During voltage sequence (for UHS SD/SDIO cards), host first sends the
voltage switch command (CMD11) to card and then host must stop the clock
at least for 5ms but currently there is a possibility (if clkgate_delay
is 0) that clock may be gated off immediately after the CMD11 response
from card and then get turned on before 5ms itself. This patch ensures
that clock is gated off at least for 5ms after receiving the card
response for voltage switch command.
Change-Id: I131b3d154adab29bef367c8ce31c2f2edd159fd2
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
With commit 0797e5f145 (mmc: core: Fixup signal voltage switch), most of
the voltage switch sequence handling is moved to MMC core framework layer
and hence the role of host controller driver is left only to provide few
callbacks (one callback to change the voltage level and one more to let
the core layer know whether the card is puling down the data lines or
not).
This patch makes all the relevant changes to msm_sdcc host controller
driver to make it work with updated MMC core framework layer.
Change-Id: Ia1620ae351318cffbc58b03988ee815c66ed80df
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The power save bit is currently enabled based on the clock
rate (clk_rate > 400KHz) within struct sdhci_msm_host. But this
clk_rate is updated with the latest value down in this function
sdhci_msm_set_clock(). So during runtime/system resume when the
card is still in initialization phase, the power save bit is
getting enabled when sdhci_msm_set_clock() is called for the
first time based on the previous rate which is wrong.
Change-Id: I05dc8a4a760f658935de3831aaf8dd3b2b996466
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
For several MoviNAND eMMC parts, there are known issues with secure
erase and secure trim. For these specific MoviNAND devices, we skip
these operations.
Specifically, there is a bug in the eMMC firmware that causes
unrecoverable corruption when the MMC is erased with MMC_CAP_ERASE
enabled.
References:
http://forum.xda-developers.com/showthread.php?t=1644364https://plus.google.com/111398485184813224730/posts/21pTYfTsCkB#111398485184813224730/posts/21pTYfTsCkB
Change-Id: I9946828b9c9063da312f95483fcc47e26585489a
Signed-off-by: Ian Chen <ian.cy.chen@samsung.com>
Reviewed-by: Namjae Jeon <linkinjeon@gmail.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Cc: stable <stable@vger.kernel.org> [3.0+]
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
Patch-mainline: v3.6
Git-commit: 3550ccdb9d
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Enable power save feature within controller by setting bit 1
in vendor specific register (0x10C). This allows controller to
disable SD clock when bus is idle to save power.
Change-Id: I916a5a414adb3f21dc3a75f3f86c3a81d6956dc8
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch enables automatic calibration for eMMC devices
in using auto-command21. This feature is disabled by default
and can be enabled using the sysfs attribute
'enable_auto_cmd21'.
CRs-Fixed: 516314
Change-Id: I020c61cb9dee56c0ebe37864e67e4753ddee1adc
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch adds Programmable Delay Line auto-calibration
support if supported by respective hosts.If the host
supports auto-calibration this change would enable
sending CMD19/CMD21 before any read operation.
CRs-Fixed: 516314
Change-Id: I8a0f51206dc0e174519dd71f0c75267a9e08e7f7
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch checks the state of the device when schedule_suspend
fails and prints the error iff pm_runtime_error or pm_runtime is
disabled.
CRs-Fixed: 529879
Change-Id: I5800bc64cdcf5859260a7f24b9773355bef2f750
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
As per specification, auto cmd error status register is valid only
when auto cmd error bit is set in Error interrupt status register.
CRs-fixed: 515513
Change-Id: Id1013e1705d8efdba0171dcad14f783607d38ef3
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Certain Hynix eMMC 4.41 cards might get broken when HPI feature is used
and hence this patch disables the HPI feature for such buggy cards.
As some of the other features like BKOPs/Cache/Sanitize are dependent on
HPI feature, those features would also get disabled if HPI is disabled.
Change-Id: I6a638ce089cbd977122e47aecb721bc3f0adf7b0
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
With the new 3.9 kernel there is a change in power up and set IO
voltage sequence due to which the driver waits for an interrupt
that never trigers. Similarly, for eMMC slot, power IRQ will not
be triggered when IO voltage is changed to 1.8V. As a temporary
workaround change the power up sequence and also change the core
layer driver to not issue set voltage request to 1.8V as eMMC will
anyways be set to 1.8V as part of power up by SDHCI driver.
Change-Id: Ibb7c48219b57693c9f3d26b062d18d6d4b6b8b71
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This change needed because for urgent data transfer request is not
supported in upstream kernel.
This support includes following patches:
1. 9b0f5ecb226647953458edc10d049014575ce565
(mmc: Add support to handle Urgent data transfer request, 2013-04-15)
2. e9382e68cfca3c6b5dc128ef197d6c6fd201f9d4
(mmc: fix read latency of urgent request, 2013-04-15)
3. c96f40ad355a41d64febe29c10fb1c5d8d249499
(mmc: core: Fix updating clock scaling statistics, 2013-04-11)
4. 29b89ca5d0aa673cdf345eeb628ea070bac157ed
(mmc: sdhci: Add stop transmission support, 2013-04-15)
5. fa436d52cd2eac88d4b257c461c41c73bfae2092
(mmc: sdhci-msm: enable stop transmission support, 2013-04-17)
6. cceca8d24734926e7b5deb124adc1c2d6a6c41dd
(mmc: sdhci: Add stop transmission support, 2013-04-24)
Change-Id: I702fef0bdcb81d410199d2feeb775d6ec1fa15e6
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
In HS400 mode a new RCLK is introduced on the interface for read data
transfers. The eMMC5.0 device transmits the read data to the host with
respect to rising and falling edges of RCLK. In order to ensure correct
operation of read data transfers in HS400 mode, the incoming RX data
needs to be sampled by delayed version of RCLK.
The CDCLP533 delay circuit shifts the RCLK by T/4. It needs to be
initialized, configured and enabled once during HS400 mode switch and
when operational voltage/clock is changed.
Change-Id: Ie7acc50cb932a7b531434ebe72f78e2e7ad27408
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The following msm platform specific changes are added to support HS400.
- Enable CDC calibration fixed feedback and sleep clock.
- Allow tuning for HS400 mode.
- Add capability to parse and configure pull settings for RCLK pin.
- Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register.
Change-Id: I1304fe0f01df493ead48bf9ff3c7baee5ab040d4
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
HS400 bus speed mode also requires tuning to be performed as done in
HS200 mode. Add the capability in host layer to perform tuning for
HS400 too.
Change-Id: I4508739dd76b1aca79f0c975fb31010c6f8ba9df
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
HS400 is a new bus speed mode introduced in eMMC5.0 specification. This
patch adds the capability in mmc core to switch to HS400 mode when both
the host and the card supports it.
Change-Id: I53ee4982eae9e5cfccafe065b532d4a2f7225d17
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The request to change the VDD I/O voltage level to high/low will
trigger an IRQ only when -
1. SWITCHABLE_SIGNALING_VOLTAGE bit 29 of SDCC_MCI_GENERICS register
is set.
2. Above condition is true and when there is a state change in VDD
bit 3 of SDHCi Host Control 2 register.
Until now, the MMC core layer issues I/O high request only after
the controller is powered up. The I/O high request is same as the reset
state of host control2 register which will never trigger an IRQ. The
driver already handles this case by ensuring that I/O voltage is set
to high as part of power up itself and thus returns immediately when
I/O high request is issued later. But in 3.10 kernel, this request is
issued even before the controller is powered up. Hence, check for
host->pwr state to avoid waiting for an IRQ that never comes.
Change-Id: I31b6723f53397be1ba151305ead89e739560eb20
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The bus speed selection code in mmc_card_init() is convoluted, refactor
the code to simplify this and make it simpler for adding new bus speed
capabilities.
Change-Id: I1ee5365eaad42298a053d0b2d64b87b64bd05c5e
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Since some systems have higher memory pressure, we limit the amount of
simultaneous test requests. The former limitation was 118, due to the
request queue size, but now we further restrict this number to half.
Change-Id: I893b9ad1b133c922f90497b0ec1f416514529fb8
CRs-fixed: 510814
Signed-off-by: Lee Susman <lsusman@codeaurora.org>
Some SDHC controllers are unable to handle data end-bit
errors in one bit mode.
This patch adds a quirk to ignore data-end-bit error in
1-bit mode in Qualcomm SDHC controllers.
Change-Id: Ica0f10573d654021449c32197b126e12bb1a3c10
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch adds wakeup event capability for sdio cards.
When a wakeup event is received during suspend, a reference
to the card devices' wakeup source is taken for 300 ms.
It is expected that the function driver would act on the
wakeup event within this time-period.
Change-Id: I80fe0c450e8d9b3df51aa181d667d94517c961dc
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch initializes wakeup source if the detected card
is a sdio card and enables the wakeup capability.
Platform drivers would have to invoke:
* pm_wakeup_event on this card device to signal a wakeup
* corresponding pm_relax have to be invoked
Change-Id: Ic8d5c98073e8ed3f676eb42fc0ce1f13a11cb40f
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
At the moment if the block layer issues an URGENT request notification
before receiving a complete on the URGENT request currently handled by
the device driver - the system crashes with a BUG_ON().
This change enables multiple block layer urgent request notification to
be handled by MMC layer by removing single notification enforcement.
CRs-fixed: 517724
Change-Id: Idfa410d0c2286146f8d58a38b5abd6886036317c
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
According to eMMC specification (4.5 onwards), CORRECTLY_PRG_SECTORS_NUM
field will reflect the accumulated packed sectors that were transferred
plus header. The header (1 sector size) is not actually written to NAND.
The fix will decrement correctly programmed sectors byte count by 1 sector
size.
CRs-fixed: 518341
Change-Id: I94a79903469c011308fcaf195fce5af5f0525026
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Some controllers can gate the clock to save power
even for SDIO cards. In such cases, an asynchronous
interrupt mechanism is used to receive interrupts
even when clocks are off.
This patch wakes up the sdio thread if interrupts
were received when clocks were off.
Change-Id: Ifcfafad251dedc992637596b6bb9349cfbca5d8b
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Implement dump_vendor_registers host operation to print the
vendor specific registers in addition to standard SDHC
register during error conditions.
Change-Id: I347e8f0373264574a80e460967afba6859607ac9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Add new host operation dump_vendor_regs to provide a
mechanism through which host drivers can dump vendor
specific registers in addition to SDHC registers
during error conditions.
Change-Id: Ifba3ddcb18c3c0917343d99fe58d5ed04b2da871
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The auto command error interrupt is not enabled now. Hence,
if there occurs a timeout when auto-cmd is in progress,
no data timeout interrupt would occur and the driver would
only timeout after the software timer expires.
This patch enables the auto command error interrupt and lets the
higher layers know of such an error, if any.
CRs-Fixed: 515513
Change-Id: I69880a72ece7730645dcfe699d58271d60cab33d
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
This patch adds support to configure regulators only if
it is defined in dts files. However, it doesn't return an
error otherwise.
Change-Id: Iac2284b2df3b3d8af623da0f17697694994b34b8
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This flag ensures that the power to the sdio card is not
cut-off. That way this can wake-up the device when required
using asynchronous interrupt mechanism.
Change-Id: Ic91bfdc93e117c5e627360a4d0ef80f661aa1b60
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch disables runtime PM for sdio cards because
the runtime PM is managed by the respective SDIO function
drivers.
The card device (if sdio card) is set as runtime active
however, the runtime PM is not enabled for the same.
The runtime PM framework ensures that a device's
parents' cannot be suspended till all of its children
are suspended.
Change-Id: Ie0778d96f91738fc14a0dc05a3430c1f382ef13c
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Provide sysfs tunables to defer PM QoS vote of default value so that
back-to-back requests wouldn't suffer from latencies caused by CPU
power collapse transition states.
Change-Id: I7180c68c1f13240faa5f432335d72e7f6b198183
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
PM QoS vote of default value mean that the CPU is allowed to move
into deepest low power mode whenever possible. Currently, if there
are back-to-back MMC requests, with a short delay, the PM QoS vote
to default value is done immediately which cause the immediate
request to have high latency as the CPU might have idle'd and moved
to deepest low power mode. To avoid this defer the PM QoS vote till
a defined timeout (pm_qos_timeout_us), so that back-to-back requests
may not suffer from additional latencies.
In addition, if the load on MMC is low, the additional latency may be
sustainable. Hence, aggressively release the vote in order to achieve
additional power savings.
CRs-Fixed: 501712
Change-Id: I82166b0ce9416eb0d519f7da26e5a96956093cb2
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
When the card is removed in mmc_sd_detect(), the card status is
marked as runtime suspended and this asynchronously triggers
runtime suspend of it's parent mmc_host class device. The
mmc_power_off() will be called from runtime suspend handler and
it races with mmc_power_off() within mmc_sd_detect(). Fix this by
acquiring mutex at the host driver when set_ios host operation
is invoked and until it is done.
CRs-fixed: 513141
Change-Id: I4e7afbe966ecbcc2c8bf746fb6cffc64b7cf252e
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
During suspend, eMMC VCC can be turned off. So instead of sending
a power off notification, send a sleep command. According to the
eMMC 4.5 specification, this is the only time where its clearly
mentioned that the VCC regulator can be turned OFF.
This has been clarified in eMMC 5.0 specification and this applies
even if PON with sleep is not sent to the card.
Change-Id: I6c424bed3158132af7f9c2a2a701af7369fd5ec7
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
The specification indicates that the tuning process is normally
shorter than 40 exections of tuning command. Hence, retry the
tuning sequence for at least 3 times before returning the error.
Change-Id: I21724a73af7b997e128b56a2600bdcb12e414996
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Now that bootloaders support sdhci mode, its possible for them
to leave the sdcc core in sdhci mode after loading the kernel
in ram and pass control to Linux for bootup. In that case if
sdcc driver was enabled, the core wont function as expected
since it happens to be in sdhci mode.
So for sdcc cores that support sdhci mode, disable SDHCi mode
before initializing the sdcc core during probe.
Change-Id: Ib9dfa7dd96d3c67979b51ea39dc4810cd44e5fd3
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
The latest SDHCI controller core v3.1.0 can handle reset in middle of an
ongoing transfer without the need to stop AHB bus transaction
separately.
Change-Id: I34d2359dd2b22696a70cc146652811cb866a1d3c
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
According to the eMMC 4.5 spec "Flushing a large amount of cached data may
take very unpredictably long time". Therefore the timeout for FLUSH should
be increased to prevent timeouts.
In case the timeout occurs HPI issued.
CRs-Fixed: 500874
Change-Id: Ib00d087d3fe2fa72f5eac096976d3f24b5e4966a
Signed-off-by: Maya Erez <merez@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Few card commands can be interrupted (using HPI command) if it takes
longer time to complete so in such case its acceptable to get the
timeout errors hence ignore them when MMC core layer request for it.
Change-Id: Ie0beb93e2a7e245703504c4a2b3672051fd4d938
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
MMC core layer have made the "bkops_busy" flag in the mmc_command
structure absolute, use "ignore_timeout" instead.
Change-Id: I0a3c2bd9acfd0255c01ebb1dd209f8866b16bbab
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Some of the time consuming operations such as BKOPS, SANITIZE, CACHE
flush/off use the SWITCH command (CMD6) but as these operations don't
have card specification defined timeout for completion, we may see
timeout errors if card doesn't complete the operation within the SW
defined timeout. If SW defined timeout is hit, above operations are
considered to be failed and no real recovery mechanism is implemented
after timeout.
Most of the above operations (BKOPS/SANITIZE/CACHE flush/off) can be
interrupted by sending the HPI (High Priority Interrupt) command to card
if they taking longer than expected. This change adds the base support
which will these operations to be HPIed after timeout.
Change-Id: Ibd9061525756aaae656b1ceeeaed62e04fb80cce
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add support for polling by providing sysfs entry. It can be
enabled/disabled, by writing 1/0 respectively to the sysfs node -
sys/bus/platform/devices/msm_sdcc.<slotno>/polling. The polling
will be available only if hardware based card detection is not
supported.
Change-Id: Ic58c36665e23cb921d76c482494a168289e83b83
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
MMC_CAP_HW_RESET capability was only referring to host driver
capability to toggle eMMC RST_n pin so if the host driver is
unable to toggle this pin, it shouldn't advertise this capability.
CRs-Fixed: 507926
Change-Id: Ia1408d95503d19ae0f7c49c7bb7905b0ddaddbd5
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
MMC_CAP_HW_RESET capability was only referring to host driver
capability to toggle eMMC RST_n pin so if the host driver is
unable to toggle this pin, it shouldn't advertise this capability.
CRs-Fixed: 507926
Change-Id: Ia7b1156c6d8e8b49d69033d580e31b972124ae97
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Change time measurements in long_sequential_test from jiffies to ktime,
and make the relevant change in test-iosched infrastructure.
In long_sequential_test we measure throughput, and the jiffies resolution
is not sensitive enough for this calculation.
Change-Id: If7c9a03c687f61996609c014e056bcd7132b9012
Signed-off-by: Lee Susman <lsusman@codeaurora.org>
In a case where, the data transfer is scheduled in PIO mode, the write
data pend feature is enabled and the command corresponding to the data
transfer is timedout, it can happen that the failure recovery mechanism
clears the internal data transfer structure but not the PIO IRQ mask.
Since the msmsdcc_irq() and msmsdcc_pio_irq() are shared IRQ handlers,
the data structures free'd in command timeout interrupt routine might
be accessed in the msmsdcc_pio_irq() causing NULL pointer dereference.
Fix this by clearing PIO IRQ mask before stopping the data transfer.
CRs-Fixed: 498700
Change-Id: If597eed5da1707b8cbfb2c9c305719bf21d0eec5
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
During the copy the last character was getting truncated.
Update the buffer copy to include all the characters.
CRs-Fixed: 499579
Change-Id: I8e1df1d1f2294e85068aebcc876bef701e088b07
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
mmc_queue_suspend() function returns the -EBUSY error if the MMC request
queue is not empty as this function was getting called from the system
suspend path which enforces time limit on the completion of the driver
suspend callback.
But recently the driver shutdown routine also started using
mmc_queue_suspend() function but in shutdown case, we would really want
to wait for the MMC request queue to be empty.
To fix above issue, this change have added new argument named "wait" to
mmc_queue_suspend() function which would tell whether it needs to wait
for the MMC request queue to be empty or not. Driver shutdown callback
will tell the mmc_queue_suspend() to wait but suspend callback won't.
CRs-Fixed: 503227
Change-Id: I86f32d68ec4c4799648785681c5776f090ea6e36
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The driver currently uses fixed timeout value from capabilities
register (bit 5-0) to calculate the timeout which is advertized
as 50MHz. But the driver uses SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK
and controls the base clock (MCLK) directly. So during card
initialization, the frequency would be 400KHz but still timeout
is calculated at 50MHz which is wrong. This patch fixes this by
using the current base clock frequency to calculate the timeout.
The controller internally multiplies the timeout control register
value by 4 with the assumption that driver always uses fixed
timeout clock value from capabilities register. Add a quirk
SDHCI_QUIRK2_DIVIDE_TOUT_BY_4 to avoid this multiplicaiton in
case base clock is used for timeout calculation.
CRs-fixed: 498159
Change-Id: I503fd16132bf17e590239997d6970b9b730d4202
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
SDCC controller provides the PWRSAVE control bit to automatically
disable the clock to card when there is no activity with card.
SDCC driver provides the compile time option to disable this pwrsave
feature completely but some of the recent driver changes ignore this
and may enable the pwrsave feature even when its not required. This
change ensures that we always check if the pwrsave is allowed or not
before really enabling it.
CRs-Fixed: 490017
Change-Id: Ica764565745ea0b54300e38157c58c0aa643291d
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SDIO 3.0 specification has added the support for asynchronous interrupt
period during which card allows the clock to be gated off.
As SDCC driver is capable of handling the asynchronous interrupt,
advertise MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE capability.
Change-Id: Id5a86bc70b7b798b23be3a0fc0d59b2db05e0409
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SDCC controller provides the PWRSAVE control bit to automatically
disable the clock to card when there is no activity with card.
During the SDCC DLL tuning, PWRSAVE is disabled to make sure that clock
is always running but once the DLL tuning is completed, currently we
enable the PWRSAVE unconditionally irrespective of its previous state.
This change ensures that we always check if the previous state of pwrsave
before really enabling it.
Change-Id: I464ab1e0db41af50550bb5a9ea9b909ee0d27dd9
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The drivers must do clk_set_rate() before the first
clk_prepare_enable() is invoked. Otherwise, the clock
driver may give a warning for such clocks.
CRs-fixed: 493685
Change-Id: I8342aa2f35d64a4dc7b8396bd9741c0aecaedc5c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Enable MMC_CAP2_CD_ACTIVE_HIGH capability if the card-detect
gpio polarity is active high.
Change-Id: I80e869dd7ecb6e24e81d1cc73ef8101c44110873
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
The current driver just enables "iface_clk" before accessing its
registers but MSM bus clocks are also required for register access
without which any register access would result in chip reset.
The MSM bus clocks can be enabled by setting vote to MSM bus bandwidth
driver. Currently, voting is being done in msmsdcc_enable/disable but these
functions will not be invoked by MMC core layer for some cases such
as mmc_power_up/mmc_power_off, which require peripheral register
access.
To resolve the above mentioned problem, bus voting and de-voting will
now be done as part of clocks management within the MSM SDCC driver.
Change-Id: I4ac514e7348a53ed2816eb4114aa17eba9cedf01
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The current driver just enables "iface_clk" before accessing its
registers but MSM bus clocks are also required for register access
without which any register access would result in chip reset.
The MSM bus clocks can be enabled by setting vote to MSM bus bandwidth
driver. Currently, voting is being done in sdhci_enable/disable but these
functions will not be invoked by MMC core layer for some cases such
as mmc_power_up/mmc_power_off, which require peripheral register
access.
To resolve the above mentioned problem, bus voting and de-voting will
now be done as part of clock management within the sdhci MSM driver
i.e., before enabling SDHC clocks and after disabling SDHC clocks.
Change-Id: Iff608fba4c58bf37a6f4ce8eb36876c79969feaf
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
At the moment only POWER_OFF_SHORT is sent to the device in case the host
is suspended. This patch adds the support of sending POWER_OFF_LONG
notification in case the device is powered off.
According to device vendors the POWER_OFF_LONG notification will shorten
the initialization time of the eMMC card during next boot up.
Change-Id: I3c6f224398450cf10463cbb316613fd430d1e8d2
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
SDCC controller provides the PWRSAVE control bit to automatically
disable the clock to card when there is no activity with card. SDCC
host controller driver always enables this feature but few SDIO
cards may require the clocks to be always running (even during
inactivity period) to raise the interrupt notification to host so
for such cards, enabling PWRSAVE fature may cause functional failures.
This change checks whether it is ok to gate the card clock before
enabling the PWRSAVE feature.
Change-Id: If36a6a20d59aeb555ece2a6959ab5407f90c787c
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SDIO 3.0 specification has added the support for asynchronous interrupt
period during which card allows the clock to be gated off.
As SDCC driver is capable of handling the asynchronous interrupt, advertise
MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE capability.
CRs-Fixed: 490008
Change-Id: Ic292f379795a821a0aa678d439eac9c2e3e560b7
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SDIO 3.0 specification has added the support for asynchronous interrupt
period during which card allows the clock to be gated off. Host needs
to first read the "Support Asynchronous Interrupt" bit in CCCR register
space to check if the card supports the feature or not. If yes and if
the host wants to enable the feature, host needs to write '1' to
"Enable Asynchronous Interrupt" bit in CCCR register space.
This change allows the host controller driver to control whether to enable
the asynchronous interrupt in card or not and if the asynchronous interrupt
is enabled then clock gating feature would be enabled for such cards.
Change-Id: I678cffb63af6a2013640a5eafa6ce9bfad8a51d6
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The original intention of polling for BKOPS completion was to give
the card enough time to perform the BKOPS before it is runtime suspended.
But as the BKOPS completion polling was happening in a different
context, it may race with card runtime/platform suspend which is quite
difficult to fix. So instead of BKOPS polling, let the runtime suspend
get deferred if the BKOPS is running on the card. Also if BKOPS is running
when platform suspend is triggered, stop the BKOPS before suspending the
card.
CRs-Fixed: 489523
Change-Id: I21e524dc2da37c4985c210abfaca00a28049c651
Signed-off-by: Maya Erez <merez@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The SDHC driver registers sdhci_led_control() with LED class device
and it gets invoked when the sysfs entry - /sys/class/leds/mmcX::
is updated. This function access SDHC Host control register (0x28)
and hence, check the driver state (runtime suspended/clocks gated)
before accessing it. Otherwise, it may result in unclocked access
resulting in system failure.
CRs-fixed: 480596
Change-Id: Icef51f02abb54316710df30429fec875030d42d9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
SDCC controller reset (SW_RST) during probe may trigger power irq if
previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we
enable the power irq interrupt in GIC (by registering the interrupt
handler), we need to ensure that any pending power irq interrupt status
is acknowledged otherwise power irq interrupt handler would be fired
prematurely.
CRs-Fixed: 487962
Change-Id: If4693869210bc8b361dadb2b68a47b6ac8707e0f
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SDCC controller on some targets like 8660, 8960, 8064 and their
variants connects with Daytona Fabric (DFAB). To achieve max.
possible performance the DFAB clock is voted to 64MHz at the
cost of some power consumption. Since we now have dynamic clock
scaling for SD/eMMC clock we can also scale the DFAB clock
accordingly without impact on performance but have some power
savings in low throughput cases.
Change-Id: Ic26541d6845b65803aa813d672ccabdfc4658d9c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Host drivers can participate in clock scaling by registering
->notify_load host operation, which allows host driver to carry out
platform specific operations for further power savings or increasing
throughput based on whether load is LOW or HIGH respectively. This
can be applicable to non-ultra high speed cards as well so remove
the check for ultra high speed cards to initialize clock scaling.
Change-Id: Icaab9520135e384f5470db68b2f25c5cdce5663a
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
msmsdcc_prep_xfer() function returns a signed integer value but
caller function msmsdcc_config_dma() is storing this value in an unsigned
integer variable which is obviously not the correct thing to do.
CRs-Fixed: 476578
Change-Id: I39159e2f4f73c7f54de359cbe4faba5e902915ff
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Wait for SW reset to be complete before proceeding further
in probe. Otherwise, any register writes immediately
after the reset would be ignored/reset.
Change-Id: If1c7f5debfca6f45a0fdb08bc759ad04b96fd86c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Large packed write request may take pretty long time to complete
causing the next read operation (if any) to wait for current write
to complete. Instead we should interrupt the current write operation
and execute waiting read operation and once the read is completed,
go back to interrupted write operation and resume it.
To support this functionality, we have added support for following new
host operations in our driver:
int (*stop_request)(struct mmc_host *host)
=> Call this op to stop the current transfer synchronously.
int (*get_xfer_remain)(struct mmc_host *mmc)
=> Call this op to take decision to interrupt ongoing
transfer or not.
In order to stop the existing write transfer, we have to first reset the
SDHCi controller which would also reset the ADMA (DMA engine). But if
the reset coincide with the ongoing burst on AHB bus then it may cause
the system NOC to go into error state and error response would be
returned for successive bus accesses from SDHCi ADMA. System NOC is
going to error state because of the terminated burst and give response
error for next accesses.
In order to workaround above mentioned issue, we need to ensure that
existing AHB burst request from SDHCi ADMA is completed before
resetting the SDHCi controller.
CRs-fixed: 479949
Change-Id: Ic4aaffb27bed560a1360bfe771b25e8b3b1fb51d
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
The version register is only 16 bits wide but we use a readl to
read it. Normally this wouldn't be a problem, but the register
offset is 0xfe, something that is not word aligned. This causes
crashes on THUMB2 kernels. Use readw instead to read the register
properly and avoid any alignment issues.
Change-Id: I3b8b14ce2f741631ef7554e3763d1d7f145077a8
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
On LPAE (Large Physical Address Extension) enabled kernel all physical
address types are 64-bit instead of 32-bit. Fix the msm sdcc driver to
accommodate this change.
Change-Id: I9ec8e1f44d803d8c3caff61e374f785185f139f7
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
In the current implementation packing is enabled according to a statically
defined trigger. This patch updates the packing control mechanism to use a
dynamically defined trigger.
The trigger's value is calculated by the relation
between the number of potential packed write requests and the mean
value of all previous potential values:
If the current potential is greater than the mean potential then
the heuristic is that the following workload will contain many write
requests, therefore we lower the packed trigger. In the opposite case
we want to increase the trigger in order to get less packing events.
In case we get an urgent request we 'punish' the packing control by
increasing the trigger.
Change-Id: I775e1582ad32a8f798e8b2bd2b3178aef357e747
Signed-off-by: Lee Susman <lsusman@codeaurora.org>
This change enables handling of urgent data transfer request by setting
MMC_CAP2_STOP_REQUEST bit of caps2 field.
In order to decrease a latency of a prioritized requests (aka Urgent
request), we might want to stop the transmission of a running "low
priority" request in order to handle the Urgent request. The urgency of
the request is decided by the block layer I/O scheduler. When the block
layer notifies the MMC layer of an urgent request and if the MMC layer is
blocked on current request to complete, it will be woken up, current
request will be stopped, any outstanding requests are reinserted back to
the block layer and urgent request execution started.
Change-Id: I542da0b2230dd8c884902f3b14c13b0744aedaa1
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Large packed write request may take pretty long time to complete
causing the next read operation (if any) to wait for current write
to complete.
Instead we should interrupt the current write operation and execute
waiting read operation and once the read is completed, go back to
interrupted write operation and resume it.
To support this functionality, we have added support for following new
host operation in our driver:
int (*stop_request)(struct mmc_host *host)
=> Call this op to stop the current transfer synchronously.
Note: stop_request implemented as empty function returning error. It is
needed to enable urgent request flow partly. The flow will not stop
undergoing request.
Change-Id: I00b7da3c7862bea62bac5605da3278137bd49070
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
The MSM SDHCI controller defines the usage of 0xF in data
timeout counter register (0x2E) which is actually a reserved
bit as per specification. This would result in maximum of
5.3 secs timeout value. For some buggy SD cards, the core
layer wants to set the data timeout to 3 secs and on our MSM
SDHCI if we configure data timeout counter value to 0xE,
then we would get only 2.67 secs. Observed data timeout errors
for CMD25 on SDR104 card. Hence program data timeout counter to
0xF, to achieve at least 3 secs timeout value.
CRs-fixed: 470661
Change-Id: Ie1e192eb9c38ca3922bb1f518073a8ff0cb57f0c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
If preset value (bit 15) is enabled in sdhci host control2
register (0x3E), then the preset value registers(0x6F-0x60)
would be used for some of the settings such as clock and
drive strength. These are HW initialized registers and are
not properly initialized by MSM SDHCI controller. This is
resulting in low throughput for some of the modes such as
DDR50/SDR50. Hence, do not enable it for MSM SDHCI.
CRs-fixed: 474518
Change-Id: Iee1241355d14e6bcebc66c3a43abf1ec94d869c3
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Ignore data timeout error for R1B commands as there will be no
data associated and the busy timeout value for these commands
could be lager than the maximum timeout value that controller
can handle.
CRs-fixed: 473435
Change-Id: I61f7463cf09648ad9fab83437abf5004effc7758
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This helps check the controller timeout logic in case of data
timeout errors.
Change-Id: Ia30757192e49865698c5f52940e1dc5d97746185
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The MMC block device ioctl path is not updated with necessary
mmc_rpm_hold and mmc_rpm_release APIs due to which the device
is either not getting resumed if it is already runtime suspended
or it is getting into runtime suspend state while the ioctl
request is still in progress. This issue would be observed only
if MMC_CAP2_CORE_RUNTIME_PM capability is defined. Fix it by
calling mmc_rpm_hold before start of ioctl and mmc_rpm_release
at the end of ioctl.
Change-Id: If1ccebcde4f797722989963a7c69ce1cfb6484fd
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
At the end of a request, the work to vote for 0 bandwidth will
be queued to workqueue but during suspend the workqueue can be
freezed causing it to not run. Hence, immediately vote for 0
bandwidth during system suspend.
Change-Id: I8e51a2b76056b280d69a8a36f6608f76a6316aa5
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Due to stop transmission mechanism to handle high priority requests,
the update of clock scaling statistics is broken as the stop command
will re-enter host through mmc_start_request() and modifies ->start.busy
timestamp. If statistics are updated after sending stop command then
the duration of the interrupted command will be left unaccounted.
CRs-Fixed: 473385
Change-Id: Id671388efbfdd16981a262c0b1e5b95d119f51ae
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Recent changes to the sdcc driver would cause bam hardware to be reset
multiple times. Whenever bam hardware is reset, there is one particular
message printed out and is not rate limited. So this change would cause
that mesage to be rate limited.
Change-Id: Ie4b70fca2225122752f540bf971d221f14e169db
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Use kernel's ftrace support to capture MMC clock frequency
transitions which can be useful for debugging issues related
to power consumption.
Usage:
mount -t debugfs none /sys/kernel/debug
echo 1 > /sys/kernel/debug/tracing/events/mmc/mmc_clk/enable
cat /sys/kernel/debug/tracing/trace_pipe
Change-Id: I25c4ee39dcbe30e7665902a9f723a5a421b55ca3
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
This patch prints out the runtime-pm state of a device
on error conditions.
Change-Id: I2f981898a572e2c7baf2410f90013fa20d1dc3f0
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
The driver is using wrong clock rate to calculate the required
bandwidth and due to this voting is happening for more bandwidth
than it is required. This is ultimately preventing system core
voltage from entering into low power mode.
The sdhci_host clock indicates the clock rate as requested by MMC
core layer and the actual rate that is set is indicated by clk_rate
within struct sdhci_msm_host. As of now, sdhci_host clock is being
used to calculate the bandwidth whereas bus-bw-vectors-bps indicates
only supported bandwidths and hence a mismatch. Fix this by using the
right clock rate which is clk_rate within struct sdhci_msm_host.
Change-Id: If7d81e44a9b479c4c8e9fbaa7e092af2afb9cb9f
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
According to eMMC specification, only commands of classes 0, 2, 4
are admitted while accessing RPMB partition. Still usage of any
other command other than CMD0, CMD6, CMD8, CMD12, CMD13, CMD15,
CMD18, CMD23, CMD25 is illegal.
If the MMC clock scaling algorithm decides to switch the clocks
while accessing RPMB partition it might need to send tuning
command (CMD21) which is illegal.
Since RPMB accesses are short and doesn't depend on throughput
bypass clock scaling while the current partion mode is RPMB.
The clock scaling statistics still take into account the duration
of access and hence able to respond quickly on the transfers made
after partition switch.
Change-Id: I422f2e6acb33ab97105944e3f7f90c3afb37ef47
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
If threaded irq is registered without the primary handler then it
must set the IRQF_ONESHOT flag or else threaded irq registration
will fail.
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The sanitize support is added as a user-app ioctl call, and
was removed from the block-device request, since its purpose is
to be invoked not via File-System but by a user.
This feature deletes the unmap memory region of the eMMC card,
by writing to a specific register in the EXT_CSD.
unmap region is the memory region that was previously deleted
(by erase, trim or discard operation).
In order to avoid timeout when sanitizing large-scale cards,
the timeout for sanitize operation is 240 seconds.
Change-Id: I975dce80ea38033b3282973d760462a1b4bb9caa
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
This patch fixes the following issues in sdhci driver
from msm 3.9 kernel -
1. gpio_get_value_cansleep() is used from atomic context
resulting in warning from gpio driver. Move it to non-atomic
context.
2. Move sdhci_enable_preset_value() in set_ios callback after
clocks are enabled otherwise it would result in access to SDHCI
registers if clocks are disabled due to clock gating or suspend.
Change-Id: I231aa6e5c02669cf1aa3f21764642fa7da9a01ff
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
MMC host ops "start_signal_voltage_switch" is called to switch the
vdd_io voltage level from high voltage to low voltage but if the vdd_io
voltage level is already set to low voltage range then there is no need
to perform the voltage switching. This patch ensures the same.
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This patch adds support to speficify the current limit of
the VDD rail for the card. This is required for supporting
SD3.0 cards.
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The SDHC core power control IRQ gets triggered when -
* there is a state change in power control bit (bit 0)
of SDHCI_POWER_CONTROL register.
* there is a state change in 1.8V enable bit (bit 3) of
SDHCI_HOST_CONTROL2 register.
* Bit 1 of SDHCI_SOFTWARE_RESET is set.
This patch addresses the following 2 issues -
The reset state of 1.8V enable bit in SDHCI_HOST_CONTROL2 is 0
which indicates 3.3V IO voltage. So, when MMC core layer tries to
set it to 3.3V before card detection, the IRQ doesn't get
triggered as there is no state change in this bit. Hence, with
the current code, the VDD IO voltage is never getting set to
3.3V. This patch fixes this issue by setting the VDD IO voltage
to 3.3V whenever SDHC gets powered up.
We get different IRQ ACK status for each of these requests -
power on, power off, IO high, IO low. As of now, the driver is
not considering the IRQ ACK for IO high and IO low requests and
is returing prematurely from check_power_status() based on the
previous ACK for power on/off requests. This is resulting voltage
switch errors during voltage switch sequence for SD/eMMC cards.
This issue is fixed by passing the request type to
check_power_status host op so that driver can wait for its
corresponding ACK from power IRQ.
Change-Id: I07707ac5df731a0d3e4abead28076f0bbbf75c0a
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
MSM SDHCI doesn't control power as specified by the Standard
Host Controller 3.0 spec. Writing to power control register/
reset register/voltage bit of host control register would
trigger an IRQ with appropriate status bits set. Hence, use
host op check_power_status after writing to power control
register to check the status and wait until the IRQ is handled.
Change-Id: Ied1a82e385547f7f5d60807fc896ea5a13084657
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
In order to improve read request latency, urgent notification allowed
anytime, when current or previous requests are existing in the mmc layer.
It is not allowed to stop following running requests:
- urgent request: block layer should serialize urgent request notification.
- read request: it can't be packed, therefore it is better
to wait for its completion.
- REQ_FUA: interruption and delay in such request will impact sync process
of upper layers.
Change-Id: Id7d1480cce2059c1f23a5f29ad8f74e858be1ee6
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
Urgent request notification stops currently running transaction
on bus.
In order to decrease a latency of a prioritized requests (aka Urgent
request), we might want to stop the transmission of a running "low
priority" request in order to handle the Urgent request. The urgency of
the request is decided by the block layer I/O scheduler. When the block
layer notifies the MMC layer of an urgent request and if the MMC layer is
blocked on current request to complete, it will be woken up.
The decision on whether to stop an ongoing transfer is taken according to
several parameters, one of them being the number of bytes already
transferred for ongoing transfer by host controller so far.
To calculate how many bytes were successfully programmed before stop,
CORRECTLY_PRG_SECTORS_NUM[245:242] parsed from EXT_CSD register. The
remainder of stopped request (and next prepared request in case it
exists) re-inserted back to the I/O scheduler to be handled after the
completion of the urgent request.
In case it is decided not to stop the ongoing transfer, MMC context will
wait for normal completion of the ongoing transfer, then already prepared
next request (if it exists) will be re-inserted back into block layer and
the urgent request fetched.
URGENT_REQUEST handling has following dependencies:
1. Host controller driver should support mmc_host op named "stop_request"
2. Block I/O scheduler should support re-insert API
3. eMMC card should support HPI (High Priority Interrupt) command
If any of the above dependencies are not met then urgent request mechanism
will not become operational.
Change-Id: Ic3fa1ca9463cc8991aefee940d8bfddf76c111d3
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
The SDHCi driver by default specifies a parameter that causes the
core layer to calculate a max discard value which will be set on the
mmc queue. Unfortunately the value calculated because of this would
be very small compared to what comes in by default. As a result of
this, any secure discard kind of operations are very slow.
Instead add quirk so that any SDHCi hosts that would like to use
the default value can do so.
Change-Id: Ifa1343c3e7f14b031da30b06203a8831ba544889
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
This patch checks the device state before starting a request.
It also prints out useful information in case of error
conditions.
Change-Id: Iaf87bb069c3ffb13c9b3f174c07c25d612bdcee9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
The BKOPS feature is supported for eMMC cards of version 4.41 and higher.
The BKOPS feature is one time programmable and once it was enabled on
a certain MMC card is cannot be disabled.
LA builds are often being used to verify phones that are targeted for
other HLOSes. Since not all the HLOSes implement the BKOPS features,
enabling this feature by default can cause instability when the phone
will be used by HLOSes other than LA.
Change-Id: I7b9eab0d04a86dfeaf7565dcda8bc9d2035fe02d
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
For read operation (writing data into system memory), the
SDCC-BAM producer will update the EOT flags while writing
data done descriptors into pipe memory. It is not necessary
that the s/w should set EOT flag in system consumer mode as
that may confuse hardware.
CRs-Fixed: 468046
Change-Id: I31988fdcfaf6c9fb9c9bfc540837513ea40e125c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Add support to disable available SDHC slots at bootup controlled via a
module param with a bit mask of slots to disable. QDSS is one use case
where SDHC slot is disabled for trace output.
Example Usage:
Passing sdhci_msm.disable_slots=1 as kernel command line argument would
disable SDHC slot 1, whereas passing sdhci_msm.disable_slots=3 would
disable both slots 1 and 2.
Change-Id: I97bc517adfe4a1a81a97a2789d77404b0f22b124
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Add support for enabling clock scaling feature and indicate
the same to MMC core layer by setting the capability
MMC_CAP2_CLK_SCALE.
Change-Id: I24f144d3f727160c302966888fb439b3a39a0dde
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The MSM SDHCI controller requires SDR104 mode to be set for HS200
cards. To handle this case, implement uhs_set_signaling so that
the mode selection for MSM SDHCI doesn't happen in sdhci driver.
Change-Id: I901dc82312b4299e86a7812dd74d3682650966a2
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Set the dma_mask to 0xffffffff to indicate full 32-bit
address space and thus avoiding unnecessary buffers bouncing
from high to low memory.
Change-Id: Idaffe14d4e54a27b15e5a5d82dad41d843714d57
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
With the new suspend mechanism in place, mmc host is suspended before
the mmc core and that results in the core layer trying to put the eMMC
card to sleep but since the host is already suspended at that point,
suspend/resume fails then.
Soon after the suspend/resume is retried but the same thing happens
causing the system to never suspend. To fix this, never let the mmc
host suspend before the mmc core.
Change-Id: I1a38bfaa188db937714b1a519a912c60830c65f9
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Add support for hardware based card detection for external
SD card slot.
Change-Id: I3e081f2eff54d6932a89f826cc85c201c52ca840
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Current mmc stack doesn't use the framework provided by power
management subsystem. It doesn't let each device suspend itself
and the pm operations are solely handled by the platform driver.
This may lead to races, since the concurrency of pm framework is
not used. The pm core does its best to reduce the probability of
a race between system suspend/resume and runtime PM by
decrementing/incrementing the usage counters of respective
devices during system-pm operations.
Moreover, it disables runtime PM altogether after suspending the
device and re-enables the same on resume.
To avoid this, the parent child relationship between the platform,
mmc_host and mmc_card devices is used. In this case, the relation
is defined as,
mmc_card -> (child of) -> mmc_host -> (child of) -> platform_dev
Each device is now responsible for its power management.
* mmc_card
-> schedules the runtime-suspend
* mmc_host
-> actually suspends/resume the host & card i.e. invokes
mmc_[suspend/resume]_host
* pltform_dev
-> disables irqs
Typically, the card device serves as a trigger for scheduling the
runtime-suspend and invoking runtime-resume.
Two new runtime-pm functions have been introduced:
* mmc_rpm_hold
-> resumes the device passed as a parameter
* mmc_rpm_release
-> suspends the device passed as a parameter
The above two functions are invoked from the below contexts:
* mmc_rescan
* bkops
* mmc-queue
Change-Id: Icf9dd34a445abfaf8dbb974ab1255feeda2581c9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
pre_req() runs dma_map_sg() post_req() runs dma_unmap_sg.
If not calling pre_req() before sdhci_request(), request()
will prepare the cache just like it did it before.
It is optional to use pre_req() and post_req().
Change-Id: I32cabddc4ec824515fa9ba4ff0ad7bce3679a3ef
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Patch-mainline: linux-mmc @ 16/04/11, 09:43
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Add the "perf" sysfs node to mmc_host class dev instead of
adding to it's parent platform device inorder to make it
compatible for all platform drivers such as SDCC and SDHC.
Change-Id: Ie830ac218b242be7da63ef3b8082404a8f2f20f5
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
In order to decrease a latency of a prioritized requests (aka Urgent
request), we might want to stop the transmission of a running "low
priority" request in order to handle the Urgent request.
URGENT_REQUEST handling has following dependencies:
1. Host controller driver should support mmc_host op named "stop_request"
2. Block I/O scheduler should support re-insert API
3. eMMC card should support HPI (High Priority Interrupt) command
If any of the above dependencies are not met then urgent request mechanism
will not become operational.
Change-Id: I976af4fa794fb0fac701fe12f249c36d78080c6e
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Vote for the MSM bus bandwidth required by SDHC driver
based on the speed and bus width of the card. Otherwise,
the system clocks may run at minimum clock speed and
thus affecting the performance.
Change-Id: Icf0c8710adbe2770f4eae283a50f4a13671f703f
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Vote for PM QOS by specifying the acceptable CPU to DMA latency
so that system can enter into the possible power states without
affecting the SDHC performance.
Change-Id: I5fcf9aa93da690c6e64ab70ea5b039ca663c80ad
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Sahitya Tummala