Avoid retrying using single block for read commands that
fail with MMC_BLK_DATA_ERR. The single block read retry
is needed only in case of a CRC error for which
MMC_BLK_ECC_ERR will be set anyway by mmc_blk_err_check().
Change-Id: Iec9487fd73ecf2bdd5e62732cd42cdb3a639d0dc
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
If SDHCi controller's native card detection functionality is disabled,
there is no need to keep the sdhci controller interrupt enabled after
the card is powered off. This should help masking any spurious controller
interrupt while clocks are disabled.
Change-Id: Iad56b3b9860983fe220fb7e52d863cfd216e5b09
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
This reverts commit b680bce536.
Spin lock recursion introduced, when SD card inserted during sdhci
transaction, because it is not enough to disable sdhci irq and power irq,
besides this card detect irq need to be disabled.
Change-Id: If6aa64e9d92aec70237ab8fe72a6ea7c212530b9
CRs-Fixed: 744511
Signed-off-by: Maya Erez <merez@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Add a new dts entry to define the CPU affinity in order to maintain
the IRQ pm_qos (Quality of Service) for targets that don't have little
cluster and allow setting the pm_qos to the little cluster,
to improve its performance.
Change-Id: Icf6125066d96331392d98a387974e54c96553306
Signed-off-by: Vince Leung <vincentl@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
The unclocked access could happen in the following scenario -
1. mmcqd thread is waiting for previously submitted io to be done
2. before this io is done, it is woken up due to is_urgent event
3. mmcqd thread is running and is processing the is_urgent event
4. Just about the same time the previously submitted io is done and
it sets is_done_rcv flag, tries to wake up mmcqd thread and release
host clock so as to gate the clocks.
If step 3 and 4 happen at the same time, then clocks will be gated off
before is_urgent is completely handled. Hence, make sure to hold the
clock before invoking get_xfer_remain and stop_request host->op.
Change-Id: If03177bf5e28cc217cc8e86b10d81d4adbab78b9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This reverts commit 3ec1ed2a8d.
The original 10ms delay is enough to reach power on from power
up. Increase delay is workaround to resovle resume Re-init
retries time out error. The root cause is additional QDSD block
would impact SD fucntionality as they are multiplex with SD
interface. If cd-gpio is HW floating and has a pulse, QDSD 100ms
search process would be triggerred is prior to SD block and SD
interface work as QDSD instead of SD.
The fix is merged, so revert the workaround.
Change-Id: I647be754de4a6a13678cbb1456a9db88c2714f94
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
The data complete interrupt is also used to indicate that a
busy state has ended. Fix a race condition between sdhci_cmd_irq()
that sets any cmd err and sdhci_data_irq() (received to indicate
end of busy state) that clears cmd error. This can happen when a
cmd err is set and finish tasklet is scheduled but sdhci_data_irq()
executes before the tasklet. The cmd err status is critical for the
tasklet handler to reset the controller's state machine. This
should be cleared only when we have successfully processed a sbc
command and are ready to submit the actual command next, not when
there is an actual cmd err.
CRs-fixed: 733074
Change-Id: I91ea2b949c34446fb629446aabb21505734e27bb
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Some SDHCi controller implementations did not require alignment
for ADMA buffers. When SDHCI_QUIRK2_ADMA_SKIP_DATA_ALIGNMENT defined,
the logic that fixes scatter gather list buffers is skipped.
CRs-fixed: 719302
Change-Id: I822b394a0ae4f9b8a132c13831c0cdf78684cb36
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
When using the _irqsave variant of spin_lock, irqs are disabled. In the
case of sdhci_request, this can result in relatively long periods of time
in which the irqs are disabled (up to at least 170us observed).
Since in this flow not all interrupts need to be disabled,
we use regular spin_locks here, and disable only sdhci-specific interrupts.
For this, introduce a new sdhci_ops function for enabling/disabling the
platform-specific power irqs.
CRs-Fixed: 709331
Change-Id: Ia9fb0498aab3053b393d677bae097fcd846d8180
Signed-off-by: Lee Susman <lsusman@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
SDCC AXI master uses 32-bit addressing so there's no need to use
64-bit descriptors. Using 32-bit descriptors instead will reduce
the memory footprint.
This change masks the 64-bit capability to force 32-bit ADMA
descriptors.
CRs-Fixed: 719303
Change-Id: Ifb8095763136bbc795227bdfcb346d1e1fae42c7
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
When eMMC cache is disabled, the card has to flush all the data in its
cache.
This change increases the timeout for cache flush operation and also uses
the cache flush timeout in cache disable operation.
Change-Id: I373050a99816c95e784a957de4271955a511b9f9
CRs-Fixed: 723701
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Add a capability to selectively increase the delay between
power_up and power_on. This delay was arrived at after performing
a series of experiments to find the minimum value. It is required
in some scenarios to avoid command timeouts during resume.
Change-Id: I857e740aa20a33e08515d054e5c9bf128db229c6
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
SDCC5 controller doesn't advertise 1.8v capability by default.
Dual voltage capability is required for SD3.0 support. Add this
capability for controllers that support this based on
device tree configuration.
Change-Id: Ie4cd6db2e7230bc22cd393c8e37d99f49c777cd0
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
If zero length ADMA descriptor with "Tran" attribute is queued to ADMA
descriptor table then host controller ADMA engine might get stuck.
Currently we are seeing zero length descriptor getting queued in for
SDIO transactions:
SDHCi driver requires that any data buffer address should be 4-byte
aligned for 32-bit ADMA and 8-bytes aligned for 64-bit ADMA. For 64-bit
ADMA, it forces 8-byte alignment for any data buffer addresses. This
aligment requirement is not an issue with eMMC/SD cards as their
transactions are always in multiple of 512-bytes (block size) and hence
sdhci driver would always get the data buffers whose address is properly
aligned.
SDIO can have transactions less than 512-bytes. Hence its quite possible
for driver to receives data buffer addresses which are not properly
aligned. And if they are not aligned, SDHCi driver bounces the non-aligned
bytes to pre-allocated aligned buffer until the rest of the data buffer
becomes aligned. But this logic has a bug where after moving the
non-aligned number of bytes to aligned buffer, it assumes that we will
always be left with non-zero number of bytes in original data buffer and
hence driver ends up queuing one more descriptor which can be of zero
length.
Fix this by checking for the remaining data length before queuing up the
next descriptor.
Change-Id: I7af77b2a2661c00f2b1da47953717b1506bdba83
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SDMA buffer boundary size parameter in block size register should only be
programmed if host controller DMA is operating in SDMA mode otherwise its
better not to set this parameter to avoid any side effect when DMA is
operating in ADMA mode operation.
Change-Id: Ia29ca4759ead2e4c9ea1d72908444a03bf205bac
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
With some devices like QRD SKUK, SD card could not support
hotplug as there is no cd-gpio, and also could not use polling
way due to power comsumption. So add nonhotplug to meet such
requirement and when SD card lost or removed manually, device
will not crash until next reboot process to detect SD card.
Change-Id: I318d3db72fc09248c5dada2fb6d69ade1bbf85cb
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
With some devices, SD card could not support hotplug as there is
no cd-gpio, and also could not use polling way due to power
comsumption. So add nonhotplug to meet such requirement and when
SD card lost or removed manually, device will not crash until
next reboot process to detect SD card.
Change-Id: Ie8ea8ec57015f36689a119249003eeaa48391393
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
* commit 'v3.10.49': (529 commits)
Linux 3.10.49
ACPI / battery: Retry to get battery information if failed during probing
x86, ioremap: Speed up check for RAM pages
Score: Modify the Makefile of Score, remove -mlong-calls for compiling
Score: The commit is for compiling successfully.
Score: Implement the function csum_ipv6_magic
score: normalize global variables exported by vmlinux.lds
rtmutex: Plug slow unlock race
rtmutex: Handle deadlock detection smarter
rtmutex: Detect changes in the pi lock chain
rtmutex: Fix deadlock detector for real
ring-buffer: Check if buffer exists before polling
drm/radeon: stop poisoning the GART TLB
drm/radeon: fix typo in golden register setup on evergreen
ext4: disable synchronous transaction batching if max_batch_time==0
ext4: clarify error count warning messages
ext4: fix unjournalled bg descriptor while initializing inode bitmap
dm io: fix a race condition in the wake up code for sync_io
Drivers: hv: vmbus: Fix a bug in the channel callback dispatch code
clk: spear3xx: Use proper control register offset
...
In addition to bringing in upstream commits, this merge also makes minor
changes to mainitain compatibility with upstream:
The definition of list_next_entry in qcrypto.c and ipa_dp.c has been
removed, as upstream has moved the definition to list.h. The implementation
of list_next_entry was identical between the two.
irq.c, for both arm and arm64 architecture, has had its calls to
__irq_set_affinity_locked updated to reflect changes to the API upstream.
Finally, as we have removed the sleep_length member variable of the
tick_sched struct, all changes made by upstream commit ec804bd do not
apply to our tree and have been removed from this merge. Only
kernel/time/tick-sched.c is impacted.
Change-Id: I63b7e0c1354812921c94804e1f3b33d1ad6ee3f1
Signed-off-by: Ian Maund <imaund@codeaurora.org>
In the current HS400 selection sequence high speed mode is entered
twice unnecessarily. Skip the first hs selection as it is also done
as part of entering high speed DDR mode.
CRs-fixed: 707453
Change-Id: Id027af977fe416056a6fbef39da1a84e41d89e53
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The platform_get_resource API may return NULL, hence check
the return value before using the mapped memory.
Change-Id: I28741554f8e1b5843671ee0d6b08bdcf8e4469c9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This change fixes pointer de-references without NULL check before.
Change-Id: I624e56513c09a2d5919cb91f650f4e2982eb3d71
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Certain Samsung eMMC meet multi read timeout, and could not
reponse status CMD anymore after that. Add long read timeout
fixup to resolve it.
Change-Id: Ibeb0e6ab3d889d48fdee91244bec720a6994b907
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
8K is the max descriptors supported by the hardware per transfer.
On normal use cases we never use that many descriptors even if
the memory is extremely fragmented. The memory allocated for these
descriptors are never freed hence wasting memory otherwise
available for the system. Reduce the max descriptors to 512 to save
memory (128K with 8K descriptors vs 8K with 512 descriptors) and
still support maximum performance.
CRs-fixed: 684185
Change-Id: Ib57ce03834d741c0fda4195a58d6b287ee9fb0a0
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Rather than using the streaming API, use the coherent allocator to
provide this memory, thereby eliminating cache flushing of it each
time we map and unmap it.
CRs-fixed: 684185
Change-Id: I615133da06a04fa23c6bca4078e484299147eb34
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Save sglist enumeration for write since identifying misalignment is only
required on read use cases.
CRs-fixed: 684185
Change-Id: Iacb362e8a9cd68d487ea6bd8ce8e56eef49f471e
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
On read, we don't need to sync the whole scatterlist and then check
whether any segments need copying - if we check first, we avoid
potentially expensive cache handling.
CRs-fixed: 684185
Change-Id: I9a07b1b1e83d0299765f80adc14bbff44f7ed114
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Markus Pargmann <mpa@pengutronix.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
Git-commit: de0b65a786ae83c8f6dfb712f65b9a36af70a981
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[venkatg@codeaurora.org: use align_bytes - 1 for alignment check]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
If the card is removed, the wakelock has to be held for
an extended period of time to enable the user-space to
respond. The code to extend the wakelock has been
duplicated. This patch removes this duplicate code.
CRs-fixed: 684724
Change-Id: I96e4e9dec46ada7853724c36f0c2c6329f696e5d
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This changes ensures that pointer to card struct is valid.
Change-Id: I11405cd7dd3a1a43fdb3010152a07c1c7944fc9d
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Instrument the sdhci driver with tracepoints to aid in
debugging issues and identifying latencies in the following
path:
* CMD completion
* DATA completion
* DMA preparation
* Post DMA cleanup
Change-Id: Ie8cd0c2fb6c1bd6ab13883123be021081f8b8f78
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Use the correct power class field from the extended CSD register
for HS400 mode as defined in the eMMC5.0 specification.
CRs-fixed: 690341
Change-Id: Ie10e35941fd3c6ee49c686f721bf5af6fcd74862
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Rather than using the streaming API, use the coherent allocator to
provide this memory, thereby eliminating cache flushing of it each
time we map and unmap it. This results in a 7.5% increase in
transfer speed with a UHS-1 card operating in 3.3v mode at a clock
of 49.5MHz.
CRs-fixed: 684185
Change-Id: I82aae6264db1ebfb87badbb223893b066ad53652
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Markus Pargmann <mpa@pengutronix.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
Git-commit: d1e49f77d7c7b75fdc022e1d46c1549bbc91c5b7
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[venkatg@codeaurora.org: use adma_desc_sz for ADMA_SIZE & align_bytes - 1
for alignment check]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The actual resume takes place when a request is received. In a
situation when mmcqd and qseecomd(rpmb) both try to resume the
device, a race is ensued. This is because mmcqd first resumes
the device and then claims the host. Ideally, if resume is in
progress in one context the resume in the other context should
be cancelled.
Claim the host before resuming the device in mmcqd context.
CRs-fixed: 697018
Change-Id: I11d33e642a9b2022f77277196de128c9ac78d334
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
commit 5027251eced6e34315a52bd841279df957f627bb upstream.
a27fbf2f067b0cd ("mmc: add ignorance case for CMD13 CRC error") produced
a cmd.flags unhandled in realtek pci host driver. This will make MMC
card fail to initialize, this patch is used to handle the new cmd.flags
condition and MMC card can be used.
Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The current vote applies to all CPUs and hence may have power
impact, especially when there are more number of CPUs. The new
IRQ specific QoS request shall update the vote only for one
CPU to which the IRQ's smp_affinity attribute is set to.
Change-Id: I55298f729949c39ebfa3eecd4746d77e40cb2e5c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
With some bad SD cards, it is possible that the error recovery
procedure goes into a state where it retries the failed command
infinitely leading to CPU hog.
Fix inifinite retries when the bad SD card isn't responding to
a command even when the SD card reset mechanism is successful.
CRs-Fixed: 671153
Change-Id: Ic6db66b571aa425aec32c82d52789c68fe0cb0e9
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
When handling a DISCARD operation, the MMC request data structure may be
freed in memory. Therefore, it can't be used to retrieve the cmd_flags
for checking if MMC_REQ_NOREINSERT_MASK is set:
(!(mq->mqrq_cur->req->cmd_flags & MMC_REQ_NOREINSERT_MASK)))).
To prevent the issue we should use the local variable of cmd_flags.
Change-Id: Idef53d5bd66fa6f1faaf79644c8efb5177c75e89
Signed-off-by: Maya Erez <merez@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Program CORE_CSR_CDC_DELAY_CFG for hardware recommended 1.25ns delay.
We may see data CRC errors if it's programmed for any other delay
value.
CRs-Fixed: 683894
Change-Id: Id7de28b7b9222c35e6b419e416f72bd8f98cbaf8
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The current timeout value is 30 sec and with this busy timeouts
are observed on few eMMC cards. Hence, increase it to 240 sec
which is already being used in IOCTL variant of sanitize command.
It helped resolve such busy timeout issues.
Change-Id: I08993ac9fb02520267b58bddee51f9c166f129ff
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
In HS400 mode, command line is still operated in SDR mode and not
DDR mode like data lines. So in order to correctly process command
responses, the hardware needs to be set appropriately or else there
will command crc or similar errors due to incorrect sampling of the
response.
Change-Id: I426ff4fc4798afae254d11a608c800dc0b7bf765
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
The newer msm sdhci's cores use a different DLL hardware for HS400.
Update the configuration and calibration of the newer DLL block.
The HS400 DLL block used previously is CDC LP 533 and requires
programming multiple registers and waiting for configuration to
complete and then enable it. It has about 18 register writes and
two register reads.
The newer HS400 DLL block is SDC4 DLL and requires two register
writes for configuration and one register read to confirm that it
is initialized. There is an additional register write to enable
the power save mode for SDC4 DLL block.
Change-Id: I20ddeaee9309c43cd51bebdfc02d70553c9d2a87
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
The only error returned by stop_request(), is returned when there is
no current request to stop. This case is handled by mmc_stop_request()
caller.
Change-Id: I09bb30593d6accefef5d550881d87b6bf603296c
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Enhance the error handling/recovery path during eMMC resume by
adding retry mechanism and by adding additional error messages
to failure cases. This may help some of the bad parts which fail
to resume sporadically.
Change-Id: I895068edb487e6a44205e0769342b2ec2c89c876
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Fix a race condition that can lead to null pointer dereference
while the MMC transfers are going on.
1) mmc_request_done() -> mmc_wait_for_data_done ->
step1: update is_done_rcv
step2: wake_up sleeping thread (mmcqd) waiting for is_done_rcv
2) mmcqd -> mmc_wait_for_data_req_done
step4: wait for is_done_rcv or is_new_req
step5: is_new_req set from block layer context and mmcqd
is woken up
step6: let's say step1 is done, so complete the current request
step7: fetch new request and issue to host layer
step8: fetch one more request and wait for previous request to
complete
In the above execution contexts, if step4-step8 happens between step1 and
step2 a null pointer dereference is observed -
[ 29.483302] Unable to handle kernel NULL pointer dereference
at virtual address 00000488
[ 29.490366] pgd = c0004000
[ 29.493054] [00000488] *pgd=00000000
[ 29.518937] PC is at do_raw_spin_lock+0x8/0x13c
[ 29.523445] LR is at _raw_spin_lock_irqsave+0x20/0x28
[ 30.108789] [<c0339cd4>] (do_raw_spin_lock+0x8/0x13c) from
[ 30.118418] [<c095d178>] (_raw_spin_lock_irqsave+0x20/0x28) from
[ 30.127445] [<c0142ef4>] (__wake_up+0x20/0x50) from
[ 30.136124] [<c0663f70>] (mmc_request_done+0x30c/0x368) from
[ 30.145932] [<c067bd98>] (sdhci_tasklet_finish+0x130/0x13c) from
Change-Id: I9a21431b5fd9bb9bbcb5c18a9895096fe845e64b
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Fix race condition between mmcqd thread and the mmc_queue_suspend
updating a shared variable mq->flags, which can lead to potential
null pointer dereference as following-
Unable to handle kernel NULL pointer dereference at
virtual address 00000020
pgd = c0004000
[00000020] *pgd=00000000
mmcqd/0: 186] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
CPU: 0 Tainted: G W (3.4.0-1251694-eng #1)
PC is at mmc_blk_err_check+0x20c/0x3b8
LR is at mmc_start_req+0x198/0x718
cpu0 | cpu1
x |= 1 | x |= 2
final value of x can be x = 1 or x = 2
Change-Id: Ie0fff6d6dba5aebb3584cba9fb98de24515c4cd8
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Set up the card detect GPIO in active configuration before
configuring it as an IRQ. Otherwise, it can be in some
weird/inconsistent state resulting in flood of interrupts.
Change-Id: I8f2344a72acbd48df745cc9b2602fe4ac6f034d4
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The following two issues are addressed with this change -
1. The current code sets SDHCI_NEEDS_RETUNING flag even for tuning
commands and it will unecessarily cause tuning to be done again
for the next read/write command. Hence, we must not set this flag
for any CRC failures to tuning commands.
2. If SDHCI_NEEDS_RETUNING flag is set and if all tuning phases
pass, then the driver attempts to change the driver type by sending
CMD6 which is a not a tuning command. The driver will thus attempt
to do re-tuning again before sending CMD6 and goes forever in a
recursive loop. Hence, clear SDHCI_NEEDS_RETUNING flag before
executing tuning.
Change-Id: Iaf3b24b93fdf655392fe02c973799e465960a495
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
If the mmc_hw_reset() fails, then host->card might be NULL in some
cases. Hence, check for reset errors and report it to the caller so
that the current request can be aborted and also check for host->card
before accessing it so as to prevent NULL pointer dereference issue.
Change-Id: Iba0f0be314474e607a40383bc0b28eef66a31d63
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This reverts and updates commit 77776fd0a4cc541b9 ("mmc: sd: fix the
maximum au_size for SD3.0"). The au_size for SD3.0 cannot be achieved
by a simple bit shift, so this needs to be implemented differently.
Also, don't print the warning in case of 0 since 'not defined' is
different from 'invalid'.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Cc: stable <stable@vger.kernel.org> # [3.12, 3.13]
Signed-off-by: Chris Ball <chris@printf.net>
Git-commit: 9288cac05405a7da406097a44721aa4004609b4d
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Change-Id: Ia19e30f1b9d793e1757a3eb3126b994df6b7a72a
[stummala@codeaurora.org: resolved merge conflicts]
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Since SD Physical Layer specification V3.0, AU_SIZE is supported up
to 0xf. So If SD-card is supported v3.0, then max_au should be 0xf.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Git-commit: 77776fd0a4cc541b9a528eacc1d31ca47eb1ae7a
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Change-Id: I140ad257098ab88ae8fab0a9cdb28130c3d4327b
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
There could be a race between suspend and mmc_rescan as follows:
At resume:
-> mmc_pm_notify
-> mmc_rescan is scheduled
Suspend is triggered:
-> mmc_pm_notify
-> wait for mmc_rescan/cancel it
-> rescan acquires wakelock if card is detected
so as to give user-space a chance to respond
-> PM framework cancels suspend since wakelock is active
Hence, release the wake-lock if its active in suspend prepare
and check for rescan_disable before acquiring wake-lock.
This prefers suspend over notifying the user-space of the status
of the card, which is fine since with suspend user-space is frozen
too.
CRs-fixed: 655281
Change-Id: I83783589f9b541d3af73931e9a7b0b144a25538e
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Enabling cache in micron devices with manufacturer ID 0xFE
is resulting in data corruption issues during power-off tests.
CRs-fixed: 654661
Change-Id: Ifcdecb26c4c75b055a128a8d9b883fc028521930
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The intention of sdhci_msm_probe() was to wait up to 1ms for
CORE_SW_RST to be set, but only a 10us timeout was passed to
readl_poll_timeout().
Correct the timeout value to be 1ms, and decrease the sleep
time between read attempts to only 10us so that it's less
than the expected wait time of 40us.
Change-Id: I7007a68232bfba76409e2dbae3060622fa5c1913
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Mmc thread is waiting for one of following events occurs:
- current running request completion (is_done_rcv)
- new request notification arrived (is_new_req)
- urgent request notification arrived (is_urgent)
or the thread received a signal. In this case none of described events
happened.
This change process the case, when mmc thread was unblocked from wait by
signal, for example system shutdown flow.
Change-Id: I0b4f0cefedc839640c162ad3cdb011d13daaee0c
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
If the last access to eMMC before runtime/system suspend is an
RPMB access, the partition type within EXT_CSD[179] will be set
to RPMB. As per specification, the deselect CMD7 and sleep CMD5
are ignored by the card and are treated as illegal commands in
this state. This causes eMMC sleep command to timeout and thus
fails runtime/system suspend. Hence, switch to default partition
config before sending deselect CMD7 and sleep CMD5.
CRs-fixed: 630894
Change-Id: I40f3fb590aeba787de8ca3356a8eed5f2780bcc1
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
eMMC and SD card specifications restrict the usage of a class of
commands while commands in other class are in progress. For example,
during erase operations the SD/eMMC spec. allows only CMD35, CMD36,
CMD38. If clock scaling is enabled and decide to scale up the clocks
it may be possible that CMD19/21 tuning commands are sent in between
erase commands, which is illegal as per specification.
Fix such illegal transactions to the card and also make clock scaling
statistics accountable only for read/write commands instead of time
consuming commands, like CMD38 erase, where transactions are independent
of bus frequency.
Change-Id: Iffba175787837e7f95bde8970f19d0f0f9d7d67d
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
This change prevents enabling cache during card init for specific
Kingstone card.
This change is workaround the problem of long timeouts for cache
operations.
Change-Id: I6be53a408c7d6422556585d4ea2f9b1c487563e0
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
When data CRC errors occur during write transactions, mmc
block layer queries the card for successful writes. If the card
reports bytes requested as bytes successfully written, the mmc
block layer will end the request with blk_end_request(). If there
is a following async request pending for execution, the request
is thrown away while handling CRC errors leading to hang in
request queue. The hang is visible when user issues a sync()
system call.
The sequence of events are as follows -
mmcqd -> fetch a request -> send it to host driver -> fetch another
request -> wait for previous request to complete -> previous request
is in error -> skip sending current request to host driver and
do error handling for previous request in error.
During the last step, after error handling is completed the mmc
block layer does not requeue the current request which is skipped
and hence the request is infinitely stuck in the driver.
Change-Id: I9528fbe3ccb5b723fcd0793f86cca43906c4c29c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Certain Kingston eMMC 4.41 cards might get broken when HPI feature.
This quirk will disable the HPI feature for such buggy cards.
There are features depending on HPI, the change will disable them:
- BKOPS support
- stop transmission flow
- CACHE_CTRL
Change-Id: Ie675f6cb0646c06458ac8eee9a38d12fbc485be5
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
After removing the SD/MMC 'card' from the driver model we
are cancelling the pending clock scaling work which accesses
card->dev. This could cause NULL pointer issue as the card
is already removed.
CRs-Fixed: 640344
Change-Id: I8c5ee817e3f116dedf0bf4fb51eb6b70d52467b7
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
On fast path, waiting for 1ms interval to poll registers cause
performance degradation. Also having 1ms delays for polling with
interrupts disabled cause considerable system latencies, hence
poll at 1us interval.
Change-Id: I40113ccf56050b3c46604112846e9b37b254d2be
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The status variable is being overwritten by label variable,
since the latter is an array of 0 length. Hence, move label
to be the last member of the structure.
CRs-fixed: 642326
Change-Id: If63d760427b729fe60731aad89144a600f2a2cb7
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
For controllers that doesn't support card insertion/removal i.e.,
when the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION is defined,
card_event() host op must not rely on present state register
to check the card's status.
CRs-fixed: 644221
Change-Id: Icff6db0d8fe17f01cf751896ae09aee215edc548
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The commit 'e2598c - mmc: sdhci-msm: improve tuning process'
introduces NULL pointer dereference bug for SD 3.0 cards
when all the tuning phases pass. It uses mmc_card_mmc(card)
for checking the card type but card is initialized after
tuning is done for SD card and thus resulting in NULL
pointer dereference issue.
CRs-fixed: 640424
Change-Id: I59a8d5f017243d8391269bc98998bb37fc44f685
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This is aimed to reduce the suspend time of sdhci-msm device.
The suspend of this device would be carried out in a separate
thread and other devices may suspend concurrently. This is
required since the mmc sub-system contributes to the major
chunk of suspend latency.
CRs-fixed: 634333
Change-Id: I7bdead2deacd96aec5201d82b143b07c470b3892
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Enables the asynchronous suspend of card and class device.
This would enable both these devices to suspend in separate
respective threads, thus allowing other devices to suspend
concurrently.
CRs-fixed: 634333
Change-Id: Ic73022ef777b4fae4b1065f92cfa19da51a99634
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
The following commits have been reverted from this merge, as they are
known to introduce new bugs and are currently incompatible with our
audio implementation. Investigation of these commits is ongoing, and
they are expected to be brought in at a later time:
86e6de7 ALSA: compress: fix drain calls blocking other compress functions (v6)
16442d4 ALSA: compress: fix drain calls blocking other compress functions
This merge commit also includes a change in block, necessary for
compilation. Upstream has modified elevator_init_fn to prevent race
conditions, requring updates to row_init_queue and test_init_queue.
* commit 'v3.10.28': (1964 commits)
Linux 3.10.28
ARM: 7938/1: OMAP4/highbank: Flush L2 cache before disabling
drm/i915: Don't grab crtc mutexes in intel_modeset_gem_init()
serial: amba-pl011: use port lock to guard control register access
mm: Make {,set}page_address() static inline if WANT_PAGE_VIRTUAL
md/raid5: Fix possible confusion when multiple write errors occur.
md/raid10: fix two bugs in handling of known-bad-blocks.
md/raid10: fix bug when raid10 recovery fails to recover a block.
md: fix problem when adding device to read-only array with bitmap.
drm/i915: fix DDI PLLs HW state readout code
nilfs2: fix segctor bug that causes file system corruption
thp: fix copy_page_rep GPF by testing is_huge_zero_pmd once only
ftrace/x86: Load ftrace_ops in parameter not the variable holding it
SELinux: Fix possible NULL pointer dereference in selinux_inode_permission()
writeback: Fix data corruption on NFS
hwmon: (coretemp) Fix truncated name of alarm attributes
vfs: In d_path don't call d_dname on a mount point
staging: comedi: adl_pci9111: fix incorrect irq passed to request_irq()
staging: comedi: addi_apci_1032: fix subdevice type/flags bug
mm/memory-failure.c: recheck PageHuge() after hugetlb page migrate successfully
GFS2: Increase i_writecount during gfs2_setattr_chown
perf/x86/amd/ibs: Fix waking up from S3 for AMD family 10h
perf scripting perl: Fix build error on Fedora 12
ARM: 7815/1: kexec: offline non panic CPUs on Kdump panic
Linux 3.10.27
sched: Guarantee new group-entities always have weight
sched: Fix hrtimer_cancel()/rq->lock deadlock
sched: Fix cfs_bandwidth misuse of hrtimer_expires_remaining
sched: Fix race on toggling cfs_bandwidth_used
x86, fpu, amd: Clear exceptions in AMD FXSAVE workaround
netfilter: nf_nat: fix access to uninitialized buffer in IRC NAT helper
SCSI: sd: Reduce buffer size for vpd request
intel_pstate: Add X86_FEATURE_APERFMPERF to cpu match parameters.
mac80211: move "bufferable MMPDU" check to fix AP mode scan
ACPI / Battery: Add a _BIX quirk for NEC LZ750/LS
ACPI / TPM: fix memory leak when walking ACPI namespace
mfd: rtsx_pcr: Disable interrupts before cancelling delayed works
clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock
clk: samsung: exynos4: Correct SRC_MFC register
clk: clk-divider: fix divisor > 255 bug
ahci: add PCI ID for Marvell 88SE9170 SATA controller
parisc: Ensure full cache coherency for kmap/kunmap
drm/nouveau/bios: make jump conditional
ARM: shmobile: mackerel: Fix coherent DMA mask
ARM: shmobile: armadillo: Fix coherent DMA mask
ARM: shmobile: kzm9g: Fix coherent DMA mask
ARM: dts: exynos5250: Fix MDMA0 clock number
ARM: fix "bad mode in ... handler" message for undefined instructions
ARM: fix footbridge clockevent device
net: Loosen constraints for recalculating checksum in skb_segment()
bridge: use spin_lock_bh() in br_multicast_set_hash_max
netpoll: Fix missing TXQ unlock and and OOPS.
net: llc: fix use after free in llc_ui_recvmsg
virtio-net: fix refill races during restore
virtio_net: don't leak memory or block when too many frags
virtio-net: make all RX paths handle errors consistently
virtio_net: fix error handling for mergeable buffers
vlan: Fix header ops passthru when doing TX VLAN offload.
net: rose: restore old recvmsg behavior
rds: prevent dereference of a NULL device
ipv6: always set the new created dst's from in ip6_rt_copy
net: fec: fix potential use after free
hamradio/yam: fix info leak in ioctl
drivers/net/hamradio: Integer overflow in hdlcdrv_ioctl()
net: inet_diag: zero out uninitialized idiag_{src,dst} fields
ip_gre: fix msg_name parsing for recvfrom/recvmsg
net: unix: allow bind to fail on mutex lock
ipv6: fix illegal mac_header comparison on 32bit
netvsc: don't flush peers notifying work during setting mtu
tg3: Initialize REG_BASE_ADDR at PCI config offset 120 to 0
net: unix: allow set_peek_off to fail
net: drop_monitor: fix the value of maxattr
ipv6: don't count addrconf generated routes against gc limit
packet: fix send path when running with proto == 0
virtio: delete napi structures from netdev before releasing memory
macvtap: signal truncated packets
tun: update file current position
macvtap: update file current position
macvtap: Do not double-count received packets
rds: prevent BUG_ON triggered on congestion update to loopback
net: do not pretend FRAGLIST support
IPv6: Fixed support for blackhole and prohibit routes
HID: Revert "Revert "HID: Fix logitech-dj: missing Unifying device issue""
gpio-rcar: R-Car GPIO IRQ share interrupt
clocksource: em_sti: Set cpu_possible_mask to fix SMP broadcast
irqchip: renesas-irqc: Fix irqc_probe error handling
Linux 3.10.26
sh: add EXPORT_SYMBOL(min_low_pfn) and EXPORT_SYMBOL(max_low_pfn) to sh_ksyms_32.c
ext4: fix bigalloc regression
arm64: Use Normal NonCacheable memory for writecombine
arm64: Do not flush the D-cache for anonymous pages
arm64: Avoid cache flushing in flush_dcache_page()
ARM: KVM: arch_timers: zero CNTVOFF upon return to host
ARM: hyp: initialize CNTVOFF to zero
clocksource: arch_timer: use virtual counters
arm64: Remove unused cpu_name ascii in arch/arm64/mm/proc.S
arm64: dts: Reserve the memory used for secondary CPU release address
arm64: check for number of arguments in syscall_get/set_arguments()
arm64: fix possible invalid FPSIMD initialization state
...
Change-Id: Ia0e5d71b536ab49ec3a1179d59238c05bdd03106
Signed-off-by: Ian Maund <imaund@codeaurora.org>
As of now we ignore CRC/INDEX command failures to tuning command
and still wait for data from card but in case the card did not
receive the command, it won't send the data. This is causing
software request timeout for tuning commands. Hence, software
must not ignore such cmd errors for tuning commands but end the
request immediately after resetting the controller for both CMD
and DATA. Also, wait for 146 MCLK cycles for card to send out the
data and thus to move to transfer state. Its corresponding phase must
also be considered as bad phase.
CRs-fixed: 625855
Change-Id: Ic8462dd9c67e4f18a3ce73d972591772be8c6d10
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Moves bus scaling code to architecture independant directory
for platform drivers.
Change-Id: Ie0d5b104882d1534fae262af85e99cc09a56ab04
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
Fix possible NULL pointer dereference within cd-gpio IRQ
handler mmc_gpio_cd_irqt(), which can potentially happen
if the card detect IRQ gets triggered before host->ops
are initialized.
CRs-fixed: 628836
Change-Id: I2f47717d338c5c7f8e7a994c28bb5c30b30286c6
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
When ADMA is disabled the max segments and max req size were not set
properly, set them right to use the driver in PIO mode.
Change-Id: I754c30c017062540335f96480d103f054cc38084
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Commit 6932a01cd (mmc: card: quirk: disable cache for Hynix card)
claims to disable cache because of data corruption issues when cache
it is enabled. In reality, the patch allows enabling of cache during
card initialization but disallow flushing of cache during suspend or
file system sync operations. This is more dangerous than without
the commit. Move the fixups for disabling cache to mmc_fixups so as
to enable the quirk during initialization itself. Also, remove obvious
warnings everytime card is initialized during runtime resume.
Change-Id: I3f71eaccf90ffdea83f418b7c05be68f5d89d227
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
In newer hardware, the tuning process is not able to always
find a reliable phase to use for sampling data. This is mostly
due to hardware. This problem manifests itself as all successful
tuning phases, which means that the phase choosen could be a bad
one but is not identified as such at the time of tuning. So in
order to work around this, rely on optional drive types implemented
by the eMMC card, in addition to the mandatory drive type (50 ohm).
By using drive types supported by the card, when all phases are
sucessful in tuning, change drive type to a different value in the
list of supported drive types and retune. This will continue for all
tuning phases until a valid one is found. After that the drive type
is reset to the default one, if changed.
Change-Id: I348fb30daa43d97c58f83f7e4a22019f94ef4954
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Get the various drive types other than the default supported
by the card.
Change-Id: I122971e4fb4a3ab98f0078ceafca3380e9c0e2d1
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
This is needed for supporting 64-bit kernel.
Change-Id: Id4f60dc15688a6f02f31d77705ad1ef0181a1ce9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
In the current code, if sdhci_check_state returns true a tasklet is
scheduled which doesn't complete the request if host->mrq is NULL,
which is the case, if sdhci is in bad state. This would make the
mmcqd thread wait for completion infinitely.
Hence, complete the request if sdhci_check_state returns true instead
of scheduling the tasklet.
CRs-Fixed: 615537
Change-Id: I8e2950c3999ac3806f9d631c52d86f0dc13b992f
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Fix the following compilation issue when CONFIG_PM_SLEEP is defined and
CONFIG_PM_RUNTIME is not defined -
error: implicit declaration of function 'sdhci_msm_runtime_suspend'
[-Werror=implicit-function-declaration]
return sdhci_msm_runtime_suspend(dev);
^
error: implicit declaration of function 'sdhci_msm_runtime_resume'
[-Werror=implicit-function-declaration]
return sdhci_msm_runtime_resume(dev);
^
cc1: some warnings being treated as errors
make[5]: *** [drivers/mmc/host/sdhci-msm.o] Error 1
Change-Id: Id720f595746888c81c07426aab0c850cbaeccf0c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
In some cases, it is possible that the hardware might trigger
an interrupt just about the same time the software tries to
reset the controller. In such case, the hardware interrupt will
be handled after the current thread release spin lock. This leads
to spurious interrupt handling after the completion of reset.
Change-Id: I75211adee1179b0636a918f5ceb68a072ad02a6c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
commit 66b512eda74d59b17eac04c4da1b38d82059e6c9 upstream.
With some SDIO devices, timeout errors can happen when reading data.
To solve this issue, the DMA transfer has to be activated before sending
the command to the device. This order is incorrect in PDC mode. So we
have to take care if we are using DMA or PDC to know when to send the
MMC command.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit f662ae48ae67dfd42739e65750274fe8de46240a upstream.
Under function mmc_blk_issue_rq, after an MMC discard operation,
the MMC request data structure may be freed in memory. Later in
the same function, the check of req->cmd_flags & MMC_REQ_SPECIAL_MASK
is dangerous and invalid. It causes the MMC host not to be released
when it should.
This patch fixes the issue by marking the special request down before
the discard/flush operation.
Reported by: Harold (SoonYeal) Yang <haroldsy@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
mmc block data can be NULL. Hence, check for NULL before
dereferencing md.
CRs-Fixed: 562259
Change-Id: I0182c216ec73347cdd2ea464f593839fffd242a9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Merge the second phase of support needed for the 8916
target into msm-3.10. This includes a couple hundred upstream
patches for ARM64 support, as well as 8916 specific driver
development.
* origin/tmp-branch: (211 commits)
ARM: dts: msmplutonium: Update the cpu release address
Revert "arm64: Fix memory shareability attribute for ioremap_wc/cache"
clocksource: arch_timer: Do not register arch_sys_counter twice
xtensa: adjust boot parameters address when INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX is selected
sched_clock: Add support for >32 bit sched_clock
sched_clock: Use an hrtimer instead of timer
sched_clock: Use seqcount instead of rolling our own
clocksource: Extract max nsec calculation into separate function
ARM: sched_clock: Load cycle count after epoch stabilizes
sched_clock: Make ARM's sched_clock generic for all architectures
of: move of_get_cpu_node implementation to DT core library
of: introduce common FDT machine related functions
of: Introduce common early_init_dt_scan
mm: allow pgtable_page_ctor() to fail
of: only include prom.h on sparc
mm: introduce helper function mem_init_print_info() to simplify mem_init()
mm: use a dedicated lock to protect totalram_pages and zone->managed_pages
KVM: Move gfn_to_index to x86 specific code
ARM: KVM: move GIC/timer code to a common location
arm64: mm: Fix PMD_SECT_PROT_NONE definition
...
Conflicts:
arch/arm/mach-msm/board-8226.c
arch/arm/mach-msm/board-8610.c
arch/arm64/kernel/asm-offsets.c
arch/arm64/kernel/fpsimd.c
arch/arm64/kernel/setup.c
Change-Id: I289996bc18d8a2782906e7db1171b48e3ee46a73
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
After the last architecture switched to generic hard irqs the config
options HAVE_GENERIC_HARDIRQS & GENERIC_HARDIRQS and the related code
for !CONFIG_GENERIC_HARDIRQS can be removed.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Git-commit: 0244ad004a54e39308d495fee0a2e637f8b5c317
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[imaund@codeaurora.org: resolve merge conflicts]
Signed-off-by: Ian Maund <imaund@codeaurora.org>
In case of illegal buffer passed down by user, return -EFAULT instead
of count.
Change-Id: I2ce2ba5e8d26245fe828e8b6f102c218125bdf3b
Signed-off-by: Lee Susman <lsusman@codeaurora.org>
Merge support needed for the ARM64 8916 target into msm-3.10.
* origin/tmp-b7dbbd5: (289 commits)
arm: add pdev_archdata for dma_mask
thermal: tsens: fix compilation warning
msm: sps: remove sps header file
defconfig: arm64: msm: enable gpio sysfs reporting
arm64: Align CMA sizes to PAGE_SIZE
msm: ipa: add 64-bit support for IPA
defconfig: msm: Enable IPC Router and QMI kernel interface
msm: kgsl: Implement ioctl_rb_issueibcmds for compat
msm: rndis_ipa: add support for 64 bit
msm: ecm_ipa: add support for 64 bit
ARM: dts: msm: Add SPI clocks for QUP1 on plutonium.
ARM: dts: msm: Configure SPI on plutonium QUP1.
msm: ipa: set dma mask of IPA device
msm: ipa: add support for compat_ioctl
msm: ipa: move out of mach tree
arm: dts: msm8916: Change property for CMA regions
arm64: Change type of dma_{alloc,free}_from_contiguous
msm: kgsl: manage active count for perfcounter read compat ioctl
ion: msm: Add custom compat ioctl
ion: Add custom_compat_ioctl
...
Conflicts:
arch/arm/mach-msm/Kconfig
drivers/platform/msm/ipa/teth_bridge.c
Change-Id: I2e5ebfd104d72a91191fef6de33e107399c17938
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
If cpu-dma-latency is not defined in dts files, set it
to 200usec
Change-Id: I27b0357b4d88842a258332250bae66efac3ee5e2
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Remove the sps header file from older location as sps
driver and clients need to use new header file from
new location include/linux.
Resolve the warnings/errors from client drivers due to
new sps header changes.
Change-Id: I1cdb87756abf3425a9bb5d8bf89cd1aa03a01716
Signed-off-by: Dipen Parmar <dipenp@codeaurora.org>
There is a new header file for 64bit platforms.
Change-Id: Iead9ccab1fd0b7249baf670e67872fcffeccf21d
Signed-off-by: Raviv Shvili <rshvili@codeaurora.org>
As a result of following fix: "mmc: core: do not reinsert prepeared
FUA and FLUSH requests in stop flow" REQ_FUA and REQ_FLUSH requests
are not reinserted back into i/o scheduler, but instead started request
execution.
This change will prevent cleaning current request pointer for such
requests.
Change-Id: I25f8706954fb538be62182c87d5fb20354696b7a
CRs-fixed: 600127
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Add support for Linux pin control framework while also supporting
the older TLMM configuration for backward compatibility
CRs-Fixed: 568232
Change-Id: Ib6b8f41fd6ced9aa62c980d7e4a73469603cbc5b
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
This change prevents enabling cache during card init for Hynix cards.
This change is workaround the problem of Hynix cards behavior for
adb reboot flow, when as a result of power cycle with cache enabled,
ext4 journal get aborted, because of meta data corruption.
Change-Id: I3198c940a334c8e5fbc3e68e0fea638e76467a75
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
With commit 0797e5f145 (mmc: core: Fixup signal voltage switch), voltage
switch sequence for UHS-I cards is broken if used with sdhci driver.
The commit expects the SD clock to be disabled when mmc_set_ios() is
issued but sdhci_do_set_ios() re-enables the SD clock for few cycles
after disabling which is a specification violation during voltage
switch sequence. This failure is observed only for a small group of
cards where they ultimately fall-back into high-speed mode even if
UHS-I modes are supported.
Change-Id: Ie275326627a84bfcd4352637a043296c01c175a6
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
During card detection within mmc_rescan(), mmc_rpm_hold() will be called
on host->class_dev before initializing the card and shall be released
after card detection. During card detection, once the card device is
added, MMC block driver probe gets called and in case that probe fails
due to block read/write cmd error, then the block driver marks that card
as removed. Later when mmc_rpm_release() is called within mmc_rescan(),
the runtime suspend of host->class_dev will be invoked immediately. The
commands that are sent during runtime would fail with -ENOMEDIUM and if we
propagate the same to rpm framework, the runtime suspend/resume for this
device will never be invoked even if the card is detected fine later on
during subsequent removal and insertion. Hence, do not report this error to
upper layers.
Change-Id: I9e60e9fb4ebc3d267cedae14aa88021000311427
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
CLK_PWRSAVE bit in vendor specific register gates the output clock to
card automatically if there are no data/cmd operations.
According the SD3.0 voltage switch sequence the host should provide
clock to the card for atleast one millisecond before DAT[3:0] lines
are pulled high by the card. In this case if power save bit is enabled
it might auto-gate clocks even before the card completes voltage
switch sequence.
Fix this by disabling power save operation when the clocks are turned
off and enable only when clock rate is >400KHz i.e., end of initialization.
CRs-Fixed: 589992
Change-Id: If82d6d2e303b8d1189b76712e514f41fe6e2cf8b
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Sahitya Tummala