This change removes quirks for Hynix cards.
These quirks were used to avoid HPI and Cache
feature for specific Hynix cards due to
issues such as data corruption.
After further discussion with the card vendor it was
decided to restore the usage of these features.
Change-Id: I3fc85064eb427f6b3b6a4a941d8251341a6137d0
Signed-off-by: Talel Shenhar <tatias@codeaurora.org>
Add trace-points for tracking pm_qos voting.
This assists in following the voting for debugging
performance related issues.
Change-Id: I5a9e886c739252043e9f28f100e0493436a0eb75
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Add support for multiple configurations of setting pm_qos
and have all pm_qos handled from the sdhci-msm driver.
This is used in order to support different hardware
architectures (cpu-to-cluster mapping), different pm_qos
requirements for read/write accesses or to compensate for
different scheduler schemes.
Change-Id: Iade1ec6058e56a7cc81322c2d997df76b7e760a6
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
commit 14460dbaf7a5a0488963fdb8232ad5c8a8cca7b7 upstream.
Current code checks "clk_delay_cycles > 0" to know whether the optional
"mrvl,clk_delay_cycles" is set or not. But of_property_read_u32() doesn't
touch clk_delay_cycles if the property is not set. And type of
clk_delay_cycles is u32, so we may always set pdata->clk_delay_cycles as a
random value.
This patch fix this problem by check the return value of of_property_read_u32()
to know whether the optional clk-delay-cycles is set or not.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
In order to boost mmc performance on various platforms,
add support for configuring whether set_wake_up_idle()
should be called on the mmc queue thread (mmcqd).
The decision will be set in each individual platform's
dts file.
CRs-Fixed: 787554
Change-Id: I3989d3f5b8228785e6d3bc49c7eb01ebf2fa2f38
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Performance of the workload largely depends on the pm qos votes.
Dynamically identify the core in which the current task is running
and apply the pm qos votes to the cluster that this core belongs to.
This ensures that the performance of the workload is not impacted and
also improves the power efficiency of the system.
Change-Id: I4d7fc5250e73b945fa2cfef63e2be18602233f53
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This reverts commit cd9ba68520.
The original change prevented cpu power collapse.
Change-Id: I9e0d0c2ff71423f9b7bec1f23d96d2340f32c4b7
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
The latest version of the SDCC core requires a change in the reset
sequence for DLL tuning. Make necessary changes as needed.
Change-Id: I69e972c08e89efebff9822de6d0e59692784652e
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Add support for multiple configurations of setting pm_qos
and have all pm_qos handled from the sdhci-msm driver.
This is used in order to support different hardware
architectures (cpu-to-cluster mapping), different pm_qos
requirements for read/write accesses or to compensate for
different scheduler schemes.
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Change-Id: I1770ec7dcb35000b64faff0592dd6d81ca2b265c
The change in pull configs might not take into effect immediately
and any value read before it is stabilized will mark incorrect
card status. This causes SD card detection to fail when inserted
for the first time. Fix this by adding enough delay after
configuring the GPIO and before reading its value.
Change-Id: I3a8455ce404988ab5eb3ed04c0f90ab6edf76d86
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
As stated by the eMMC 5.0 specification, a chip should not be rejected
only because of the revision stated in the EXT_CSD_REV field of the
EXT_CSD register.
Remove the control on this value, the control of the CSD_STRUCTURE field
should be sufficient to reject future incompatible changes.
Change-Id: I655a59004e7e4997c12077d3a267e71344f10b66
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Git-commit: 03a59437ef6b6ad7fb0165cb9b96c08d6bf057fc
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Switch to using pr_err_ratelimited in order to avoid
flooding the logs in case of error function gets
called repeatedly.
Change-Id: I636dc933915127a43ad4da87a565f8f585e6df90
Signed-off-by: Talel Shenhar <tatias@codeaurora.org>
commit 2836766a9d0bd02c66073f8dd44796e6cc23848d upstream.
Sleep in atomic context happened on Trats2 board after inserting or
removing SD card because mmc_gpio_get_cd() was called under spin lock.
Fix this by moving card detection earlier, before acquiring spin lock.
The mmc_gpio_get_cd() call does not have to be protected by spin lock
because it does not access any sdhci internal data.
The sdhci_do_get_cd() call access host flags (SDHCI_DEVICE_DEAD). After
moving it out side of spin lock it could theoretically race with driver
removal but still there is no actual protection against manual card
eject.
Dmesg after inserting SD card:
[ 41.663414] BUG: sleeping function called from invalid context at drivers/gpio/gpiolib.c:1511
[ 41.670469] in_atomic(): 1, irqs_disabled(): 128, pid: 30, name: kworker/u8:1
[ 41.677580] INFO: lockdep is turned off.
[ 41.681486] irq event stamp: 61972
[ 41.684872] hardirqs last enabled at (61971): [<c0490ee0>] _raw_spin_unlock_irq+0x24/0x5c
[ 41.693118] hardirqs last disabled at (61972): [<c04907ac>] _raw_spin_lock_irq+0x18/0x54
[ 41.701190] softirqs last enabled at (61648): [<c0026fd4>] __do_softirq+0x234/0x2c8
[ 41.708914] softirqs last disabled at (61631): [<c00273a0>] irq_exit+0xd0/0x114
[ 41.716206] Preemption disabled at:[< (null)>] (null)
[ 41.721500]
[ 41.722985] CPU: 3 PID: 30 Comm: kworker/u8:1 Tainted: G W 3.18.0-rc5-next-20141121 #883
[ 41.732111] Workqueue: kmmcd mmc_rescan
[ 41.735945] [<c0014d2c>] (unwind_backtrace) from [<c0011c80>] (show_stack+0x10/0x14)
[ 41.743661] [<c0011c80>] (show_stack) from [<c0489d14>] (dump_stack+0x70/0xbc)
[ 41.750867] [<c0489d14>] (dump_stack) from [<c0228b74>] (gpiod_get_raw_value_cansleep+0x18/0x30)
[ 41.759628] [<c0228b74>] (gpiod_get_raw_value_cansleep) from [<c03646e8>] (mmc_gpio_get_cd+0x38/0x58)
[ 41.768821] [<c03646e8>] (mmc_gpio_get_cd) from [<c036d378>] (sdhci_request+0x50/0x1a4)
[ 41.776808] [<c036d378>] (sdhci_request) from [<c0357934>] (mmc_start_request+0x138/0x268)
[ 41.785051] [<c0357934>] (mmc_start_request) from [<c0357cc8>] (mmc_wait_for_req+0x58/0x1a0)
[ 41.793469] [<c0357cc8>] (mmc_wait_for_req) from [<c0357e68>] (mmc_wait_for_cmd+0x58/0x78)
[ 41.801714] [<c0357e68>] (mmc_wait_for_cmd) from [<c0361c00>] (mmc_io_rw_direct_host+0x98/0x124)
[ 41.810480] [<c0361c00>] (mmc_io_rw_direct_host) from [<c03620f8>] (sdio_reset+0x2c/0x64)
[ 41.818641] [<c03620f8>] (sdio_reset) from [<c035a3d8>] (mmc_rescan+0x254/0x2e4)
[ 41.826028] [<c035a3d8>] (mmc_rescan) from [<c003a0e0>] (process_one_work+0x180/0x3f4)
[ 41.833920] [<c003a0e0>] (process_one_work) from [<c003a3bc>] (worker_thread+0x34/0x4b0)
[ 41.841991] [<c003a3bc>] (worker_thread) from [<c003fed8>] (kthread+0xe4/0x104)
[ 41.849285] [<c003fed8>] (kthread) from [<c000f268>] (ret_from_fork+0x14/0x2c)
[ 42.038276] mmc0: new high speed SDHC card at address 1234
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Fixes: 94144a465d ("mmc: sdhci: add get_cd() implementation")
Cc: <stable@vger.kernel.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
mmc unit test is run by writing to a debug-fs entry, in
which the mmc_block_test_data structure is kept as private
pointer in the file object.
This private pointer was incorrectly casted to seq_file and
the mmc_block_test_data was extracted from its private data
resulting in a bad pointer.
Fixed the code to properly extract the mmc_block_test_data
structure.
Change-Id: I8a9fea6b45b621b3b7c0abc7aaa078d340dc1c6b
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
The eMMC card can go into "reset state" due to several
reasons and without host involvement,
e.g. low voltage detection.
This kind of eMMC card reset requires eMMC host to
re-initialize the eMMC card.
In case of eMMC card reset, eMMC card firmware sets its
state to "reset state" which allows CMD0 only.
In case the eMMC host is in the middle of FLUSH request it will
get timeout which will cause the driver to requeue the flush
request and try it later on.
The problem with this is that no one is going to initialize
the eMMC card to move out of "reset state", hence, the flush
request will keep on failing over and over again.
This commit adds a device reset for the case where flush request
fails due to timeout.
Change-Id: Ic268e13cb19d0cdce0070174bf7847e6253e4513
Signed-off-by: Talel Shenhar <tatias@codeaurora.org>
Unit tests submit large requests of 512KB made of 128 bios.
Current allocation was done via kmalloc which may not be able
to allocate such a large buffer which is also physically contiguous.
Using kmalloc to allocate each bio separately is also problematic as
it might not be page aligned. Some bio may end up using more than a
single memory segment which will fail the mapping of the bios to
the request which supports up to 128 physical segments.
To avoid such failure, allocate a separate page for each bio
(bio size is single page size).
Change-Id: Id0da394d458942e093d924bc7aa23aa3231cdca7
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Current test-iosched design enables running only a single test
for a single block device.
This change modifies the test-iosched framework to allow running
several tests on several block devices.
Change-Id: I051d842733873488b64e89053d9c4e30e1249870
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
This change adds a read-modify-write logic to BKOPS feature enable.
It is required in order to avoid overriding other fields defined
in BKOPS_EN register.
Change-Id: I689f5cd14d9ec1bb881f503a0418026a59e6c197
Signed-off-by: Talel Shenhar <tatias@codeaurora.org>
Some system physically doesn't support 1.8v, even if the sdhci
host support it. With no-1-8-v, SDHCI_QUIRK2_NO_1_8_V will be
set, and SDR104, SDR50, DDR50 capability will be removed which
work at 1.8v.
Change-Id: Ica88896e9db566c0fc7abb044ab6601023dcb8a2
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
Sanitize command should never be issued with timeout argument of 0,
cause then it invokes timeout.
Moreover, sanitize command should not be called from routines that
does erase/trim/secure-discard commands, but only from a routine that
issues the sanitize specifically.(mmc_blk_issue_sanitize_rq)
Change-Id: I2fc9d17d876de3440f7cdee5fce0158a919c7c6f
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
Currently there was only 1 cpu_dma_latency value which
we pass from DT for pm_qos due to which certain I/O use
cases have power/performance impact.
This patch adds support for dynamic Qos using clk scaling.
Using clk_scaling algo we dynamically decide which Qos value
to request for (i.e. Performance/Init/Power_save_mode).
Pass cpu-dma-latency table with 3 values from DT, which can
be used by sdhci layer to update pm_qos dynamically.
This patch also has backward compatibility with platforms that
does not support dynamic Qos and only pass 1 value from DT.
3 values in DT for following states of sdhci (for dynamic Qos)
1. SDHCI_PERFORMANCE_MODE -- least cpu_dma_latency
2. SDHCI_PERFORMANCE_MODE_INIT -- avg val
3. SDHCI_POWER_SAVE_MODE -- higher then avg.
may get updated with default val
based on sdhci_[enable/disable]
Change-Id: Ibce1681e9087c944a827bedb4bf406701b8ff959
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Include one more state of MMC_LOAD_INIT when resume (which
calls for mmc clk init algorithm) is called
to notify sdhci with SDHCI_PERMORMANCE_MODE_INIT.
Change-Id: I80661d7c9a927ed16925c0b9c00ac7abec608cee
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
During platform driver probe we call mmc_start_host in sdhci_add_host,
which could start the mmc_rescan work immediately and trigger a runtime
suspend. This creates a race condition where the clocks could be turned off
even before the probe has completed leading to unclocked register access.
CRs-Fixed: 770843
Change-Id: I77ae36f805e496d56ed96db3ccaa83f2c37c926c
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
SANITIZE is an operation performed by the storage device and its purpose
is to delete its unmap memory regions.
This change adds support for the SANITIZE capability.
Change-Id: Id409cb99b0b65dcc45d505cef80340df93fa36b1
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Change the rclk delay value to 0.9ns since testing shows
that the valid window may vary for different platforms and the
default value (1.25ns) might fall outside the valid window.
CRs-Fixed: 766702
Change-Id: I039d61b96bb86731471c4efb27b8c7bda1a7bb8c
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
We should keep either one of CDR_EN or CDR_EXT_EN enabled.
So correct this logic in toggle CDR function.
CRs-fixed: 759398
Change-Id: Ic137ae2a28e912ab131644ff9d81e41f4256dd05
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Currently we enable CDR for every read command including
for tuning procedure which is not correct (as CDR if
enabled might correct the phase during tuning and we
wont be able to detect the correct phase during tuning).
So, disable CDR for read tuning commands.
CRs-fixed: 759398
Change-Id: I051b6e3b204dde22cdc973759c3e32d0a81c369a
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
PM QoS request type PM_QOS_REQ_AFFINE_CORES specifies for
which CPU cores the voting will be done by the cpu affinity
mask. Define the cpu mask in the DT to be used for the voting
so it can be customized for each target.
Change-Id: Iea745e4ad60cd16fb7bf6df1b5e2447b52944e70
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
commit d1419d50c1bf711e9fd27b516a739c86b23f7cf9 upstream.
Current code erroneously fill the last byte of R2 response with an undefined
value. In addition, the controller actually 'offloads' the last byte
(CRC7, end bit) while receiving R2 response and thus it's impossible to get the
actual value. This could cause mmc stack to obtain inconsistent CID from the
same card after resume and misidentify it as a different card.
Fix by assigning dummy CRC and end bit: {7'b0, 1} = 0x1 to the last byte of R2.
Fixes: ff984e57d3 ("mmc: Add realtek pcie sdmmc host driver")
Signed-off-by: Roger Tseng <rogerable@realtek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Currently there is one rare case where suspend thread trying
to suspend sdhci-msm waits infinitely for pwr_irq interrupt
from hardware which never gets raised and thus watchdog barks
happens.
Change this waiting to wait_for_completion_timeout.
Change-Id: Ic4e9bca91b5496409b4afe2be2892c83aa390e95
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Only 1.8V is used on IO pad lines for eMMCs' on msm platforms. So this
means for any SDHC core on msm platforms used with eMMCs' should have
PAD_PWR_SWITCH bit set indicating that 1.8V is used for IO lines. So far
this did not matter as all eMMCs' SDHC pads were single voltage and the
PAD_PWR_SWTICH bit did not make a difference.
But when a SDHC core that supports dual voltage pad is used for
initializing eMMC, the BUS_ON pwr_irq generated would cause the pad
to be set at a logical HIGH in the driver (as it should since the
bus is being turned ON) but then the driver does not set or clear
the PAD_PWR_SWITCH for eMMCs which causes the communication between
the host and card to break down. So even though the IO pad is driven
at 1.8V, the host is not told that it should switch to 1.8V IO from
3.0V (default).
This does not matter for SD cards for when they are turned ON, they always
start with 3.0V on IO pad. But for eMMC instead of not setting or clearing
the PAD_PWR_SWITCH bit when the bus is turned ON, check the voltage being
supplied on the IO pad and based on that set or clear the PAD_PWR_SWITCH.
Change-Id: I7756731760298c6766d00a22160c6328faaaf4a7
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Recently we observed an interrupt timeout issue on SDIO use case,
that was caused by a SW bug in the preparation of the ADMA descriptor
table.
Dumping out the descriptor information in requests timeouts, will help
to quickly debug such issues in the future.
Change-Id: Ifa18e514df3fdb2e5808dd7e7b54deed467b1d35
Signed-off-by: Maya Erez <merez@codeaurora.org>
Rate limit sdhci_dumpregs() prints to avoid unnecessary
and exessive logging which can sometimes lead to watchdog
timeouts (especially due to bad cards).
Change-Id: Ib6be6d563e47c2d2e9e1b6b0410c2c45712a9b17
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Avoid retrying using single block for read commands that
fail with MMC_BLK_DATA_ERR. The single block read retry
is needed only in case of a CRC error for which
MMC_BLK_ECC_ERR will be set anyway by mmc_blk_err_check().
Change-Id: Iec9487fd73ecf2bdd5e62732cd42cdb3a639d0dc
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
If SDHCi controller's native card detection functionality is disabled,
there is no need to keep the sdhci controller interrupt enabled after
the card is powered off. This should help masking any spurious controller
interrupt while clocks are disabled.
Change-Id: Iad56b3b9860983fe220fb7e52d863cfd216e5b09
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
This reverts commit b680bce536.
Spin lock recursion introduced, when SD card inserted during sdhci
transaction, because it is not enough to disable sdhci irq and power irq,
besides this card detect irq need to be disabled.
Change-Id: If6aa64e9d92aec70237ab8fe72a6ea7c212530b9
CRs-Fixed: 744511
Signed-off-by: Maya Erez <merez@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Add a new dts entry to define the CPU affinity in order to maintain
the IRQ pm_qos (Quality of Service) for targets that don't have little
cluster and allow setting the pm_qos to the little cluster,
to improve its performance.
Change-Id: Icf6125066d96331392d98a387974e54c96553306
Signed-off-by: Vince Leung <vincentl@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
The unclocked access could happen in the following scenario -
1. mmcqd thread is waiting for previously submitted io to be done
2. before this io is done, it is woken up due to is_urgent event
3. mmcqd thread is running and is processing the is_urgent event
4. Just about the same time the previously submitted io is done and
it sets is_done_rcv flag, tries to wake up mmcqd thread and release
host clock so as to gate the clocks.
If step 3 and 4 happen at the same time, then clocks will be gated off
before is_urgent is completely handled. Hence, make sure to hold the
clock before invoking get_xfer_remain and stop_request host->op.
Change-Id: If03177bf5e28cc217cc8e86b10d81d4adbab78b9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This reverts commit 3ec1ed2a8d.
The original 10ms delay is enough to reach power on from power
up. Increase delay is workaround to resovle resume Re-init
retries time out error. The root cause is additional QDSD block
would impact SD fucntionality as they are multiplex with SD
interface. If cd-gpio is HW floating and has a pulse, QDSD 100ms
search process would be triggerred is prior to SD block and SD
interface work as QDSD instead of SD.
The fix is merged, so revert the workaround.
Change-Id: I647be754de4a6a13678cbb1456a9db88c2714f94
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
The data complete interrupt is also used to indicate that a
busy state has ended. Fix a race condition between sdhci_cmd_irq()
that sets any cmd err and sdhci_data_irq() (received to indicate
end of busy state) that clears cmd error. This can happen when a
cmd err is set and finish tasklet is scheduled but sdhci_data_irq()
executes before the tasklet. The cmd err status is critical for the
tasklet handler to reset the controller's state machine. This
should be cleared only when we have successfully processed a sbc
command and are ready to submit the actual command next, not when
there is an actual cmd err.
CRs-fixed: 733074
Change-Id: I91ea2b949c34446fb629446aabb21505734e27bb
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Some SDHCi controller implementations did not require alignment
for ADMA buffers. When SDHCI_QUIRK2_ADMA_SKIP_DATA_ALIGNMENT defined,
the logic that fixes scatter gather list buffers is skipped.
CRs-fixed: 719302
Change-Id: I822b394a0ae4f9b8a132c13831c0cdf78684cb36
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
When using the _irqsave variant of spin_lock, irqs are disabled. In the
case of sdhci_request, this can result in relatively long periods of time
in which the irqs are disabled (up to at least 170us observed).
Since in this flow not all interrupts need to be disabled,
we use regular spin_locks here, and disable only sdhci-specific interrupts.
For this, introduce a new sdhci_ops function for enabling/disabling the
platform-specific power irqs.
CRs-Fixed: 709331
Change-Id: Ia9fb0498aab3053b393d677bae097fcd846d8180
Signed-off-by: Lee Susman <lsusman@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
SDCC AXI master uses 32-bit addressing so there's no need to use
64-bit descriptors. Using 32-bit descriptors instead will reduce
the memory footprint.
This change masks the 64-bit capability to force 32-bit ADMA
descriptors.
CRs-Fixed: 719303
Change-Id: Ifb8095763136bbc795227bdfcb346d1e1fae42c7
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
When eMMC cache is disabled, the card has to flush all the data in its
cache.
This change increases the timeout for cache flush operation and also uses
the cache flush timeout in cache disable operation.
Change-Id: I373050a99816c95e784a957de4271955a511b9f9
CRs-Fixed: 723701
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Add a capability to selectively increase the delay between
power_up and power_on. This delay was arrived at after performing
a series of experiments to find the minimum value. It is required
in some scenarios to avoid command timeouts during resume.
Change-Id: I857e740aa20a33e08515d054e5c9bf128db229c6
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
SDCC5 controller doesn't advertise 1.8v capability by default.
Dual voltage capability is required for SD3.0 support. Add this
capability for controllers that support this based on
device tree configuration.
Change-Id: Ie4cd6db2e7230bc22cd393c8e37d99f49c777cd0
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
If zero length ADMA descriptor with "Tran" attribute is queued to ADMA
descriptor table then host controller ADMA engine might get stuck.
Currently we are seeing zero length descriptor getting queued in for
SDIO transactions:
SDHCi driver requires that any data buffer address should be 4-byte
aligned for 32-bit ADMA and 8-bytes aligned for 64-bit ADMA. For 64-bit
ADMA, it forces 8-byte alignment for any data buffer addresses. This
aligment requirement is not an issue with eMMC/SD cards as their
transactions are always in multiple of 512-bytes (block size) and hence
sdhci driver would always get the data buffers whose address is properly
aligned.
SDIO can have transactions less than 512-bytes. Hence its quite possible
for driver to receives data buffer addresses which are not properly
aligned. And if they are not aligned, SDHCi driver bounces the non-aligned
bytes to pre-allocated aligned buffer until the rest of the data buffer
becomes aligned. But this logic has a bug where after moving the
non-aligned number of bytes to aligned buffer, it assumes that we will
always be left with non-zero number of bytes in original data buffer and
hence driver ends up queuing one more descriptor which can be of zero
length.
Fix this by checking for the remaining data length before queuing up the
next descriptor.
Change-Id: I7af77b2a2661c00f2b1da47953717b1506bdba83
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SDMA buffer boundary size parameter in block size register should only be
programmed if host controller DMA is operating in SDMA mode otherwise its
better not to set this parameter to avoid any side effect when DMA is
operating in ADMA mode operation.
Change-Id: Ia29ca4759ead2e4c9ea1d72908444a03bf205bac
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
With some devices like QRD SKUK, SD card could not support
hotplug as there is no cd-gpio, and also could not use polling
way due to power comsumption. So add nonhotplug to meet such
requirement and when SD card lost or removed manually, device
will not crash until next reboot process to detect SD card.
Change-Id: I318d3db72fc09248c5dada2fb6d69ade1bbf85cb
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
With some devices, SD card could not support hotplug as there is
no cd-gpio, and also could not use polling way due to power
comsumption. So add nonhotplug to meet such requirement and when
SD card lost or removed manually, device will not crash until
next reboot process to detect SD card.
Change-Id: Ie8ea8ec57015f36689a119249003eeaa48391393
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
* commit 'v3.10.49': (529 commits)
Linux 3.10.49
ACPI / battery: Retry to get battery information if failed during probing
x86, ioremap: Speed up check for RAM pages
Score: Modify the Makefile of Score, remove -mlong-calls for compiling
Score: The commit is for compiling successfully.
Score: Implement the function csum_ipv6_magic
score: normalize global variables exported by vmlinux.lds
rtmutex: Plug slow unlock race
rtmutex: Handle deadlock detection smarter
rtmutex: Detect changes in the pi lock chain
rtmutex: Fix deadlock detector for real
ring-buffer: Check if buffer exists before polling
drm/radeon: stop poisoning the GART TLB
drm/radeon: fix typo in golden register setup on evergreen
ext4: disable synchronous transaction batching if max_batch_time==0
ext4: clarify error count warning messages
ext4: fix unjournalled bg descriptor while initializing inode bitmap
dm io: fix a race condition in the wake up code for sync_io
Drivers: hv: vmbus: Fix a bug in the channel callback dispatch code
clk: spear3xx: Use proper control register offset
...
In addition to bringing in upstream commits, this merge also makes minor
changes to mainitain compatibility with upstream:
The definition of list_next_entry in qcrypto.c and ipa_dp.c has been
removed, as upstream has moved the definition to list.h. The implementation
of list_next_entry was identical between the two.
irq.c, for both arm and arm64 architecture, has had its calls to
__irq_set_affinity_locked updated to reflect changes to the API upstream.
Finally, as we have removed the sleep_length member variable of the
tick_sched struct, all changes made by upstream commit ec804bd do not
apply to our tree and have been removed from this merge. Only
kernel/time/tick-sched.c is impacted.
Change-Id: I63b7e0c1354812921c94804e1f3b33d1ad6ee3f1
Signed-off-by: Ian Maund <imaund@codeaurora.org>
In the current HS400 selection sequence high speed mode is entered
twice unnecessarily. Skip the first hs selection as it is also done
as part of entering high speed DDR mode.
CRs-fixed: 707453
Change-Id: Id027af977fe416056a6fbef39da1a84e41d89e53
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The platform_get_resource API may return NULL, hence check
the return value before using the mapped memory.
Change-Id: I28741554f8e1b5843671ee0d6b08bdcf8e4469c9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This change fixes pointer de-references without NULL check before.
Change-Id: I624e56513c09a2d5919cb91f650f4e2982eb3d71
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Certain Samsung eMMC meet multi read timeout, and could not
reponse status CMD anymore after that. Add long read timeout
fixup to resolve it.
Change-Id: Ibeb0e6ab3d889d48fdee91244bec720a6994b907
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
8K is the max descriptors supported by the hardware per transfer.
On normal use cases we never use that many descriptors even if
the memory is extremely fragmented. The memory allocated for these
descriptors are never freed hence wasting memory otherwise
available for the system. Reduce the max descriptors to 512 to save
memory (128K with 8K descriptors vs 8K with 512 descriptors) and
still support maximum performance.
CRs-fixed: 684185
Change-Id: Ib57ce03834d741c0fda4195a58d6b287ee9fb0a0
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Rather than using the streaming API, use the coherent allocator to
provide this memory, thereby eliminating cache flushing of it each
time we map and unmap it.
CRs-fixed: 684185
Change-Id: I615133da06a04fa23c6bca4078e484299147eb34
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Save sglist enumeration for write since identifying misalignment is only
required on read use cases.
CRs-fixed: 684185
Change-Id: Iacb362e8a9cd68d487ea6bd8ce8e56eef49f471e
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
On read, we don't need to sync the whole scatterlist and then check
whether any segments need copying - if we check first, we avoid
potentially expensive cache handling.
CRs-fixed: 684185
Change-Id: I9a07b1b1e83d0299765f80adc14bbff44f7ed114
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Markus Pargmann <mpa@pengutronix.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
Git-commit: de0b65a786ae83c8f6dfb712f65b9a36af70a981
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[venkatg@codeaurora.org: use align_bytes - 1 for alignment check]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
If the card is removed, the wakelock has to be held for
an extended period of time to enable the user-space to
respond. The code to extend the wakelock has been
duplicated. This patch removes this duplicate code.
CRs-fixed: 684724
Change-Id: I96e4e9dec46ada7853724c36f0c2c6329f696e5d
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This changes ensures that pointer to card struct is valid.
Change-Id: I11405cd7dd3a1a43fdb3010152a07c1c7944fc9d
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Instrument the sdhci driver with tracepoints to aid in
debugging issues and identifying latencies in the following
path:
* CMD completion
* DATA completion
* DMA preparation
* Post DMA cleanup
Change-Id: Ie8cd0c2fb6c1bd6ab13883123be021081f8b8f78
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Talel Shenhar